ben Posted September 19, 2012 Report Share Posted September 19, 2012 Hi all,I started pondering over a 3d engine for the papilio, using VGA output of a TV wing, rendering "on the fly" rather than in a bitmap buffer (nintendo ds style, for those who know about it), to avoid the need for external memory.A bit of thinking got me to believe that flat polygons with z-buffering was within grasp, but that texturing seemed very ambitious, as it requires a division for each drawn pixel (and a fast memory to store the texture: one access per pixel as well). As a first prototype, I also excluded alpha blending, lighting, backface culling, and z-culling (although the last one is easy) And, of course, forget about custom shaders So far I've implemented and tested the "pre-process" phase: projection of the 3d points on the 2d screen, and precomputing stuff to make the line by line rendering of triangles easier and faster (this is actually the hardest part). I also implemented all the parts of the rendering pipeline, but i have not tested it yet, and not started the (hard) work of integrating it and synchronizing it with the display.A few technical details:- target resolution is 256*240 (double lines in 640*480 VGA) ;- all computations are done in 18bit fixed point arithmetic, to fit the DSP48A1 blocks. 8 bits for the fractional part seem to give good results ;- maximum pipelining in the preprocess phase allows a throughput of 1 point every 3 cycles and 1 triangle every 6 cycles (I might slow it down a bit to save space) ;- if no bad thing happen, drawing should be 1 pixel every cycle : with a 100MHz drawing clock (which seems reasonable), we'd get a theoretical maximum of 100MHz/15kHz ~ 6600 pixels per line.Only real tests will confirm it, but the last bit makes me believe this will be able to display several hundreds of triangles in real-time. The hard part will be updating the input data in real-time too.I've written a HTML5 implementation (attached file, tested on Firefox, should work on other navigators), to check that the 18 bits fixed point arithmetic was giving decent results (it does), and as a reference for the HDL implementation.BenEDIT: VHDL code at https://github.com/ben0109/Papilio-3d Link to comment Share on other sites More sharing options...
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