Using IP cores in designs.


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How does everybody feel about use of IP cores in projects where the source is to be made available to others? - things like DCMs and block RAMs.

I can see how there are issues when you don't have clear ownership of the content (e.g. ROM images), but that isn't an issue in this case.

I'm trying to work out the best way to put a project up on my wiki that contains a lot of tables implement in block RAM and am wondering what works for others?

Should I be using primatives ant INIT strings? should I provide .coe files? should I use data2mem and keep any data out of the VHDL source?

Be interested in your views...


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If it's just DCM and BRAM, then there's probably no need to use the Xilinx core generator. Pretty much every published arcade game has a DCM and BRAMs for storing ROMs so do what they do. I think this also leads to a cleaner design as I find the core generators pollute the source files with all sorts of directories and files that are frankly not necessary.

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I have a generator that converts plain binary files and implements a VHDL single or dual-port memory, without instantiating any specific BRAM component.

It works for any data and address sizes (dual-port memory is however restricted to same data size in both ports).

Perhaps this suits you ? You can either provide the conversion tool, or just the VHDL output.


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In terms of licensing, here is an example from the NeTV project where IP cores are being distributed as part of the source tree.

The following notice is present:

"The files in this directory tree are auto-generated by the Xilinx IP Core
Generator System.
The configuration of the IP embodied in these files is the expression of
Andrew "bunnie" Huang's thoughts and these thoughts are licensed in a
CC-BY-SA 2.0 fashion. The copyright notice is located here instead of
in the file, since the configuration files are stored in a machine-
manipulated format that is not suitable for insertion of copyright notices.
The generation of the IP from these configurations is guided by the requirements
of Xilinx's IP Core Generator System."

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