Is TECS implementation possible?


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I am coming over from and wondering, is it possible to implement the computer described in TECS (and here for ease, quoted from http://nand2tetris-q...0.html#a3517367):

Transistor count: (By cadet1620 over at the nand2tetris forums)

CPU---------------------1 528

Memory decoding----253

RAM16K---------------4 538 299

ROM32K---------------2 097 088

Screen buffer---------2 793 339


Computer--------------9 430 507

Basically, the way it works, is it has a RAM16K for variable memory, a ROM32K for instruction memory, and the screen is mapped into the upper 8K of the RAM16K, just before the keyboard, which is mapped onto the upped 16 bits of the memory.

So my question really is, is it possible to implement this in Papilio One (I guess I will need the 500K version, but I was considering buying that anyway.)

Thank you!

(If something is not clear, ask, and if it is in the wrong place, then please move it, or if it has been answered, I apologise I did not find it.)

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Short answer... almost. But on a board with even a small external memory it is a piece of cake.

The long answer - Memory is the problem. The Spartan 3E 500 has 360kbits (40k bytes) of block RAM, and about 9k bytes if all the logic blocks are reconfigured as 16 bit RAM. Your numbers indicate that you need 56k bytes of RAM. Given that the sizing (-250 or -500) is the number of thousands of "equivalent gates" the CPU and memory decode logic is not an issue.

If you can have even a small amount of SRAM external to the FPGA the project would be completely possible - you could use the on-chip Block RAM as the ROM and frame buffer.

But if all you want to do is to Implement Tetris, using 48k of memory is over the top - if you could work with 16K of ROM then it will work perfectly in a Papilio One 500k

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