craiglindley Posted August 6, 2012 Report Share Posted August 6, 2012 Hello,I'm a rank newbie to FPGAs and the various design languages. I've been studying the J1 forth core and pretty much understand most of the Verilog code. The following construct however has puzzled.I understand that dsp is the data stack pointer and that it is 5 bits wide for the 32 words making up the data stackreg [4:0] dsp; // Data stack pointerHere I understand the data stack offset is extracted from the instruction as a 2 bit valuewire [1:0] dd = insn[1:0]; // D stack deltaThis expression is what I don't understand_dsp = dsp + {dd[1], dd[1], dd[1], dd};Can anyone enlighten me about what this is doing?Thanks in advance Link to comment Share on other sites More sharing options...
magnusk Posted August 7, 2012 Report Share Posted August 7, 2012 Well, not seeing the rest of the code, this looks like dd is sign-extended from two bits to 5 bits (since the most significant bit of dd is replicated 3 more times to make it a five bit value) and then added to dsp. Link to comment Share on other sites More sharing options...
craiglindley Posted August 7, 2012 Author Report Share Posted August 7, 2012 magnuskI'm sure you are correct. Now it makes sense because dd is the signed data stack offset. Thanks you Link to comment Share on other sites More sharing options...
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