Using existing Verilog code

[bug]

I have a small IP core from a previous project written in Verilog that I'd like to use alongside the AVR8 core.  Although I've used both Verilog and VHDL, I'm somewhat at a loss as to using them together.  While it appears possible to mix code in a simulation, it's unclear from Xilinx documentation whether the ISE can synthesisze them together.  Has anyone performed this successfully or is it necessary to convert all code to VHDL?

[Jack Gassett]

Hey Bug,

The tools are great about using both Verilog and VHDL in a design.

Just add your verilog file to the project, click on it, and choose the option to make the instantiation template. It will give you the VHDL you need to instantiate the Verilog file in your VHDL file.

Jack.