bug Posted May 29, 2012 Report Share Posted May 29, 2012 I have a small IP core from a previous project written in Verilog that I'd like to use alongside the AVR8 core. Although I've used both Verilog and VHDL, I'm somewhat at a loss as to using them together. While it appears possible to mix code in a simulation, it's unclear from Xilinx documentation whether the ISE can synthesisze them together. Has anyone performed this successfully or is it necessary to convert all code to VHDL? Link to comment Share on other sites More sharing options...
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