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When using the AVR8 softcore, how much RAMB is left on a 500k?

The datasheet is confusing me as well as the fact I created a 24k x 8 bit dual port SRAM with the IP Core wizard and put it on my schematic and hooked it up to the AVR8 I/O and got no errors generating the programming file.

I would assume if I exceeded the devices available RAMB it would error during the build.

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Sorry for late reply, I stayed up real late Sunday night working on schematic stuff and that blew up Monday for me. :)

The AVR8 uses 10 2K BRAM's leaving the following:

  • Papilio One 250K has 12 BRAM blocks leaving 2 BRAM blocks free.
  • Papilio One 500K has 24 BRAM blocks leaving 14 BRAM blocks free.

The free BRAM blocks can be used to increase the Program Code space of the AVR8 or for user applications.

You can look at the summary reports after doing synthesis to see how many BRAM blocks were used.


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I kept running into "design won't fit" and read the datasheet again and I think you weren't looking at 3E devices, it states:

Device      Columns    RAMB/Column  RAMB Total      RAMB Bits Total

XC3S500E      2                10                    20                  368,640

I dropped my design from using 12 RAMB down to 10 and now it fits :)

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