Bit -> SVF

[Guest brentbxr]

Hey Jack,

I was just wondering; I tried looking at your papilio loader to try and understand but I couldnt quite grasp it. So I was wondering if you wouldnt mind pointing me in the right direction. I am using a DP BBv2 to upload svf files to my fpga. I was wondering how your papilio-loader takes a .bit file and turns it into a .svf file for loading onto the board. Or am I way off here

I am really starting to get into FPGA's. Currently I do not own a papilio but I started playing with FPGA's by uploading custom svf files to my OLS. When a friend of mine designed his own FPGA dev board and offered to sell me one of his 500k gate spartan-3a dev boards at cost I couldnt turn it down. Its the cheapest FPGA development board I have ever seen, although not quite newbie friendly... Anyways so now im trying to get deep into the FPGA game; I quickly decided to invest into a papilio 250 to use for everyday testing and only use my 500k for bigger tasks; because you cannot really plug it into a Breadboard or anything; it has tiny FL cables!! its horrible to learn with; so it turned out a bad decision but it kept me long enough to decide I want to continue with FPGAs and the Papilio is perfect.

[Guest brentbxr]

I have been debating heavily on getting a papilio. The only thing stopping me is the price I paid is alot less then what I would pay for your equivielnt (sort of; its not as user friendly; but the specs are a bit better on my board). My friend siad he was in the middle of developing an even BETTER board so I told him I would venture into this new board with him (as in handle some of the cost) if he also helped make it suite my needs (He wants to learn FPGA PCB design; I want to learn FPGAs...) so hes putting on all these toys like memory and ethernet and this and that... but hes not doing anything besides super super tiny FLO 20 pin cable connectors to output maybe 1/3 the available IO... that does me no good. see the chat:

<##notsayingwho##> and my design is mostly getting my feet wet with board design for spartan6

<Brent Reamer> exactly; you can do that; while also making it friendly for me

<Brent Reamer> you want to lean board design with it; I want to learn fpgas with it :3

<##notsayingwho##> lol yeah

<Brent Reamer> although

<Brent Reamer> a papilio is pretty cheap

<##notsayingwho##> As a rough budgetary estimate, this board will be a bit more $$ lol

<##notsayingwho##> whats the specs on that

<Brent Reamer> im paid quite well

<Brent Reamer> ill link you

<##notsayingwho##> i can almost guarantee this beats anything but a few high end dev boards

<##notsayingwho##> i mean, it wont outperform the Atlys

<##notsayingwho##> this is basically a stripped down version of that using the 25k cell instead of the 45

<##notsayingwho##> 64MB DDR instead of 128MB DDR2

<Brent Reamer> its a spartan 3a

<##notsayingwho##> i have more flash though

<##notsayingwho##> oh

<##notsayingwho##> this is a spartan6 lol

<##notsayingwho##> your choice of XC6SLX25 in -2 speed or XC6SLX16 in -3 speed

<##notsayingwho##> the 25 in -3 would be ideal but digikey doesnt stock it

<##notsayingwho##> so basically the choice is less gates but higher clock frequencies

<##notsayingwho##> or more gates but slower

<##notsayingwho##> they're footprint compatible so the decision can be made any time up to assembly

<Brent Reamer> http://store.gadgetfactory.net/index.php?main_page=product_info&cPath=1&products_id=25

<##notsayingwho##> i have two of each in inventory now

<##notsayingwho##> and yeah, this thing is a massive improvement over that

<Brent Reamer> oh yeah

<Brent Reamer> but still

<Brent Reamer> just the fact its newbie friendly

<Brent Reamer> its almost worth it

<##notsayingwho##> Yeah, i may borrow a few ideas from that

<##notsayingwho##> i have to look into how to do multi-source jtag

<##notsayingwho##> as i dont wnat to use the ftdi ONLY

<Brent Reamer> one of his coolest ideas is see the funky header pattern

<Brent Reamer> those are kinda like the arduino deal

<Brent Reamer> where you can add on

<##notsayingwho##> there's a lot less IO pins

<Brent Reamer> but then again

<Brent Reamer> your not thinkging about that

<##notsayingwho##> i want a lot of toys onboard

<Brent Reamer> 

<Brent Reamer> me tooo!

<##notsayingwho##> lets see, xc3s500e is 9312 LUTs, 20 block RAM, 20 multiplier, 4 DCM

<Brent Reamer> although ever my head at the moment, not forever

<Brent Reamer> 

<##notsayingwho##> XC6SLX25 is 15,032 LUTs but they're 6-input rather than 4-input

<##notsayingwho##> which makes them, by xilinx's metrics, equivalent to 24,051 spartan3a LUTs

<Brent Reamer> 

<##notsayingwho##> then 52 block RAM and 38 multipliers

<##notsayingwho##> four DCMs and two PLLs

<Brent Reamer> :OOOOO

<Brent Reamer> o

<##notsayingwho##> http://i.imgur.com/txdYP.png

<##notsayingwho##> my handy dandy xilinx fpga comparison chart

<Brent Reamer> thats just the FPGA tho; thats so good about the specs if you cant use um

<##notsayingwho##> and oh, there's more

<##notsayingwho##> my board will have 64MB of DDR RAM

<##notsayingwho##> 128MB NAND flash

<##notsayingwho##> both on 8-bit interfaces

<Brent Reamer> :/

<Brent Reamer> still if you cant breakaway from the board itself; it does you no good.

<##notsayingwho##> SPI flash for booting off, either 8 or 16 mbits (need to see how much i need for the LX25)

<##notsayingwho##> a FT232, possibly an FT245

<##notsayingwho##> 20 pin ribbon header for GPIO

<##notsayingwho##> 100mbit ethernet

<Brent Reamer> :/

<##notsayingwho##> using an ENC624J600 controller (most of the heavy lifting off board)

<##notsayingwho##> eight LEDs

<##notsayingwho##> so far one reset button but i'll likely add some more for general input

So im buying a papilio. a 250k as i already have a 500k FPGA i could always merge the code over if i needed too and use FLO to a secondary board.

[Jack Gassett]

Hello Brentbxr,

Sorry for the late response, I've had the flu since Thursday and have been out of commision.

Ok, for the bit to svf question, the papilio loader is able to directly load a bit file over jtag. There is no need for the svf format. SVF is generally used when you are using an embedded microcontroller to load a design to the FPGA like we do with the OLS.

Your friends board sounds very exciting, I encourage him to keep working on it, but I will share some of my experience with making a BGA based design. I had a Spartan 3A board that used a BGA chip, and I ended up scraping it because they are very difficult to have manufactured for a reasonable price in small quantities. I was able to hand solder a small amount of boards but with BGA rework is very difficult. The Spartan 6 chips he is talking about using only come in BGA packages and the DDR memory he will be using is difficult to work with too. So, it is a very worthy and challenging project, but I would be aware that it is a very ambitious design to be learning with. I want to encourage rather then discourage, but I also want to make you aware of the difficulties with pulling off the proposed design. There are two factors that make the design difficult, the BGA and DDR.

Jack.