Forth on a Papilio


Recommended Posts

Hi all,

I wanted to add cheap, generic interactivity to VHDL projects, to replace  AVR8 sketches, which are great but expensive, and not extendable "in situ" (you need to compile the new sketch and flash your FPGA)

My goal is to provide a full Forth system, that allows the control and programming of FPGA projects through a UART console, without taking too much of the FPGA resources. Forth is good for that because it is very simple, produces very compact code (99% calls to subroutines) and allows the on-the-fly compling of new code on a live system.

To keep things small and fast, I designed a custom processor, with two stacks and only two general purpose registers, with a simple, RISC-like, machine code. The "machine" itself is very small (~7%  of a Papilio 500), and uses only 3 ram blocks (1 for stacks, 2 for program/data memory) It seems to work fine, except for the custom UART, which is still a bit buggy (timing  problems -- a shame at 9600 bauds...)

It's designed to be easily extensible, using memory mapped devices, so you can use it as an interface to your cores.

The Forth system itself is still very beta, but you can already define words and do some simple arithmetic and io. I implemented  a basic "compiler/assembler" and a simulator (both in Java).

Next steps are 1) complete the Forth system and 2) debug the thing thoroughly so it can be used seriously. V0 is on GitHub, at

And more info on Forth on


This post has been promoted to an article

Link to comment
Share on other sites


This sounds totally awesome! It is totally something I could see myself getting into. I've always looked at the picoblaze and wished for something small but I have no desire to code in assembly. This seems like a very good idea to provide a small and versatile way to implement control logic. I really like that you can just upload your code over the serial port. Are there any existing resources like IDE's or compilers that this can work with?

I really look forward to seeing where this goes and we will get a post up on the blog about this.


Link to comment
Share on other sites

New version, rewrote for the J1 Forth pocessor (see, thanks to Jack.

Thumbs up to James Bowman, who kindly let me reuse his Verilog code (j1.v) : the resulting code is smaller, faster and uses less fpga resources.

I also rewrote the compiler, so you can build a custom system (with/without interactivity, with/without on the fly compiling support etc.)

For the most daring, the git repo is up to date (, with a ready-to burn bit file (final.bit, for a Papilio 500)

Beware : no docs yet, and the Forth system itself is still *very* crude. but you can do some arithmetic if you like (use '__print_word' rather than '.')


Link to comment
Share on other sites

  • 6 months later...


This topic is now archived and is closed to further replies.