Memory controller hints.


hamster

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I've got my memory controller to work at 12.5ns with all reads and writes that are completed in a single cycle. Hints are

- Use a DDR2 output for the Write Enable signal to generate a (slightly underspec) 6.25ns write pulse.

- Set mem_nWE to be 'FAST' while mem_addr and mem_data is set to 'SLOW'. In theory this advances the pulse by approx 1ns, so to the SRAM it runs from 5.25ns to 11.5ns of the 12.5ns write cycle.

- Make sure that you enable the "Pack the I/O Latches/Registers into IOBs" option in "Implement Design" to get crisp signals.

My code is on http://hamsterworks.co.nz/mediawiki/index.php/Papilio_Plus/SRAM_test if you want it...

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Hi Jack,

I've got my SRAM  tester working at 100 MHz - see http://hamsterworks.co.nz/mediawiki/index.php/Papilio_Plus/SRAM_test_2

The design work was very tricky for me - a real learning exercise for me.

The web page includes a write-up on the design features - and as it exploits the SRAM's hold up time it is tricky to verify in the simulator.

Mike

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  • 1 month later...

Hi Jack,

I've got my SRAM  tester working at 100 MHz - see http://hamsterworks.co.nz/mediawiki/index.php/Papilio_Plus/SRAM_test_2

The design work was very tricky for me - a real learning exercise for me.

The web page includes a write-up on the design features - and as it exploits the SRAM's hold up time it is tricky to verify in the simulator.

Mike

Mike: any chance you can get me the prebuilt files for this ? (ndc,ngc, so on). I'm having some trouble with timings, just want to cross my timing details with your own. I'm getting a high delay on the 270deg clock, perhaps that's the problem.

Truth is I'm using the whole FPGA, and when you do that timing becomes more complex:

Number of occupied Slices:                  600 out of    600  100%

Alvie

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There seems to be something there, but I am not able to download it....

Care to send to me by email (alvieboy@alvie.com) ? Also, if you could share your timing generator that would help. Although it seems i'm almost there with not much trickery (except an added delay on reads).

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