Testbench for the SRAM module.


Recommended Posts

I've written a test bench that simulates the first 32 bytes of the SRAM.

It also logs (to the iSim console) if the following occurs:

when the write enable pulse is too short

  • when  the data setup times for a write is too short

  • when  the address bus changes when write enable is active

  • It outputs 'X's during the access time, allowing you to see when you capture data before it has settled.

Find it at http://hamsterworks.co.nz/mediawiki/index.php/SRAM_testbench 

Hope it helps somebody

Link to comment
Share on other sites


This topic is now archived and is closed to further replies.