Guest MikeSmith Posted November 13, 2011 Report Share Posted November 13, 2011 Speaking as a software guy trying to learn more about logic synthesis, there's a gaping hole in the "getting started" material for both ZPUino and Papilio; specifically, there's nothing that covers how you get from "edit the VHDL/Verilog" to "run the uploader tool". What do I install? How do I run it? How do I debug the process? These are probably all things that an experienced logic designer knows, but from the perspective of someone trying to get started with e.g. the Papilio Linux VM as a starting point, there are no tools or any guidance at all for this phase of the process. Given that this is the major distinguishing aspect of the Papilio platform, it seems like I must be missing something, but I can't actually find anything at all that covers this gap. = Mike Link to comment Share on other sites More sharing options...
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