"getting started" guide extension - synthesising new bit files

Guest MikeSmith

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Guest MikeSmith

Speaking as a software guy trying to learn more about logic synthesis, there's a gaping hole in the "getting started" material for both ZPUino and Papilio; specifically, there's nothing that covers how you get from "edit the VHDL/Verilog" to "run the uploader tool".

What do I install?  How do I run it?  How do I debug the process?

These are probably all things that an experienced logic designer knows, but from the perspective of someone trying to get started with e.g. the Papilio Linux VM as a starting point, there are no tools or any guidance at all for this phase of the process.  Given that this is the major distinguishing aspect of the Papilio platform, it seems like I must be missing something, but I can't actually find anything at all that covers this gap.

= Mike

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You're right, perhaps we ought to add some more examples.

What you need basically is:

A synthesis tool - go to www.xilinx.com and download latest ISE suite for free (you still have to register)

Either use the UI to create your project, or use the command line tools provided to synthesize, map and place your design.

Upload your generated bitfile using papilio_loader.

I did write a few docs about HDL, but none related to the process. Maybe I should do so...

ZPUino includes a few makefiles that generate (99%) of the design.

PS: I sent you an email earlier today regarding the git clone issue. Not sure you received it.


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