Guest anirbax Posted October 19, 2011 Report Share Posted October 19, 2011 Hi guys, I downloaded the Xilinx ISE Webpack, but realize that I don't need fancy GUI and 5GB download and multiples licences. I have a lot of ASIC experience and I just need: 1) A Verilog synthesis tool to generate Spartan 3E .bit files, and some static timing checks 2) An HDL simulator, e.g., CVer 3) Papilio Programmer command line to download the bit file onto Papilio 4) The HDL, pin assignments and constraints I can write using my fav. text editor (gvim) Now, I have (2, 3, 4) but (1) is what I don't know how to do on the command line using the ISE. Does anyone know what are the command line tools for bit gen and the static timing that come with ISE? Thanks, Anirban Link to comment Share on other sites More sharing options...
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