Guest AtomSoft Posted August 31, 2011 Report Share Posted August 31, 2011 I have a 24 bit signal (internal) which i want to use to collect data from 3 bytes then split the data into 2 other signals which vary in size. I get 3 bytes from UART @ 19200bps. I have tested the uart from Xilinx to work at that speed using the example code from papilio. --i want to load dout into fullt 3 times while shifting the oldest byte to the left. fullt <= fullt(15 downto 0) & dout; -- is this ok? --the above is called 3 times then the below happens --take bits 8-19 (need only 12 bits) add <= fullt( 19 downto 8 ); --take lower 7 bits and place in char signal char <= fullt( 6 downto 0); I get a warning : Signal <fullt<23:20>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Need some understanding of why ? since i am shifting data into 23:20 it should be used still. Link to comment Share on other sites More sharing options...
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