Why is this getting trimmed

[Guest AtomSoft]

I have a 24 bit signal (internal) which i want to use to collect data from 3 bytes then split the data into 2 other signals which vary in size.

I get 3 bytes from UART @ 19200bps. I have tested the uart from Xilinx to work at that speed using the example code from papilio.

    --i want to load dout into fullt 3 times while shifting the oldest byte to the left.

    fullt <= fullt(15 downto 0) & dout; -- is this ok?

    --the above is called 3 times then the below happens


    --take bits 8-19 (need only 12 bits)

      add <= fullt( 19 downto 8 );


    --take lower 7 bits and place in char signal

      char <= fullt( 6 downto 0);

I get a warning :

Signal <fullt<23:20>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Need some understanding of why ? since i am shifting data into 23:20 it should be used still.

[alvieboy]

Care to share the whole process ?

[Guest AtomSoft]

sure, not sure why i didnt before...

signal byteCount : integer range 0 to 4:=0;

signal fullt : STD_LOGIC_VECTOR (23 downto 0);

signal readit : std_logic := '0';

....

    update_ram:process(byteCount,dout,data_present,fullt) is begin

        

        

        if(data_present = '1')then

            wrea <= (others => '0');

            readit <= '1';

            byteCount <= byteCount + 1;

            fullt <= fullt(15 downto 0) & dout;

        end if;

        

        if(byteCount = 3)then

            byteCount <= 0;

            add <= fullt( 19 downto 8 );

            char <= fullt( 6 downto 0);

            wrea <= (others => '1');

        end if;

        

        readit <= '0';


    end process update_ram;

[ben]

Well, it's exactly as the compiler says, the upper bits (20-23) are never used: they are assigned, but never read, so the compiler drops them. And since you don't use them, you shouldn't care.

I am more surprised that it doesn't complain about readit, which is assigned twice in the process (in the first 'if', and in the common part at the end)

If I get your idea, readit is a reset signal to let the UART know that you've read the byte, and that it should set 'data_present' to 0. The problem is, there is no timing in VHDL. It might work in simulation, as the signal changes are instantaneous, but I doubt it works on a real chip. Most probably, you'll end up reading the same byte over and over until the UART catches up on the "readit" change and finally sets data_present to 0.

Shouldn't you clock your processes ? Then you know exactly when and how often they are executed, and you can eventually synchronize several processes. In your case, you should just use the same clock for the UART control and your process.

update_ram(clk,...) begin

  if rising_edge(clk) then

    if data_present=1 then

      ...

    else

      readit=0

    end if;

    if byteCount=3 then

      ...

    end if;

end process;

[Guest AtomSoft]

ah i knew i forgot something.. will add the clock part asap... also i thought perhaps since i was doing:

fullt <= fullt(15 downto 0) & dout;

that would count as the upper bits being used. But i guess its smart

[Guest AtomSoft]

Also why do i get a error if i try:

signal fullt : STD_LOGIC_VECTOR (19 downto 0);

it says it wont fit ... ill leave it at 23 downto 0 but its funny

[alvieboy]

fullt <= fullt(15 downto 0) & dout;

You cannot do this unless in a synchronous process.

Ouside synchronous processes you only have combinatorial logic. So basically you are saying here that:

fullt(16) = fullt(15),

fullt(15) = fullt(14),

...

fullt(0) = dout;

This means either all fullt bits are set to dout, or you're generating something weird.

Note that VHDL is just a description language - everything will boil down to flip flops, combinatorial logic and dedicated entities after synthesis.

So what you want is:

process(clk) begin

if rising_edge(clk) then

fullt <= fullt(15 downto 0) & dout;

end if;

end process;

This will create an 16-bit shift register.

[Guest AtomSoft]

Thanks i forgot to post i got it working like that. Ill post a new video soon!

Its for the vga thing.. basically a UART to VGA text only for now