ben Posted August 15, 2011 Report Share Posted August 15, 2011 Hi all, trying to get the CPLD of my C/RAM wing to work without buying an outrageously expensive JTAG cable from XILINX, I made a XSVF player that turns the papilio into a kind of JTAG cable. More precisely, instead of uploading directly the jedec (resp. bit) file into the cpld (resp. fpga) through a JTAG cable, you ask iMPACT to create a XSVF file. Then you feed this file to the Papilio through UART, which turns it into the proper JTAG signals to program the device. It's still very beta, but it seems to work: at least the answers from the cpld in the programming phase are correct. Using a 9600 bauds connection (very beta, I said), programming a Xilinx 9572 CPLD (180k XSVF file) takes around 2 minutes, counting the one minute idling to match the erase timings. With a 115200 bauds connection and a finer clock control, it could take 30 seconds or less. The papilio runs an AVR C program (loosely based on the one Xilinx provides for 8502) and the client is a unix C program. I tried to use a more portable language (python) for the client, but getting the serial port to work properly was too much of a hassle. It's extremely simple though -- it's basically a "read bytes from a file, push them on the serial port" loop -- so getting it to run on windows should be easy. I'll put the source on github sometime tomorrow (after I've done some more testing and cleaned it up a little) Link to comment Share on other sites More sharing options...
This topic is now archived and is closed to further replies.