New to FPGA

[Guest AtomSoft]

Hello all, my name is Jason. I want to learn FPGA and plan to be as helpful as possible to the community but for me to do that i need some resources... Any good info on books i can use to learn some VHDL ?

As of now i program in C mostly but know ASM... I use PIC micros and ARM mostly. Im no professional but i seem to learn things quick... I have a website AtomSoftTech.com also a online store. It doesnt have a thousand items but it has some useful parts for great prices.

On my site i usually post all my projects and such with source and schematics. So feel free to drop by.

My site is still new. All my work is on http://atomsoft.wordpress.com/ still since it was my blog. I might move all the data over but still thinking about it.

I created some code to test a blinking LED out but  as of right now i have no hardware to test on. Also i have to slow the clock down and was wondering if someone can point me in the right direction.

I hear i am supposed to use a DCM to divide the clock down but how can i get it down to 1hz - 2hz from 32mhz. I saw your video on 32 to 96 DCM and was great, but a tutorial on how to divide the clock would be awesome!

Anyway as stated i dont own the hardware yet but plan on purchasing it this week from a US supplier. (Papilio One) (500k) so if someone could simply recommend a book on VHDL (not verilog) it would be greatly appreciated and also any comments on this blink code would be great...

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity BlinkLed is

    Port ( LED_01 : out  STD_LOGIC;

           OSC_IN : in  STD_LOGIC;

              RESET : in STD_LOGIC);      

end BlinkLed;


architecture Behavioral of BlinkLed is

    signal state : std_logic;

begin

    

    process(OSC_IN, RESET) is begin

    

    if(RESET = '1') then

      state <= '0';

    elsif(rising_edge(OSC_IN)) then

      state <= not state; 

    end if; 

        

    end process;

    

    LED_01 <= state;


end Behavioral;

UCF File contains:

NET OSC_IN                        LOC = "P89"  | IOSTANDARD = LVTTL; # 32.00 MHz oscillator

NET LED_01                       LOC = "P86"  | IOSTANDARD = LVTTL | DRIVE = 20 | SLEW = FAST | PULLUP ; #

[Jack Gassett]

Hello AtomSoft,

Welcome to the Papilio community, we are glad that you are joining us. Good luck on your online store, it looks like it is off to a nice start.

The Papilio Playground is a publically editable wiki and has a collection of recommended books and reading for beginners.

Then book that personally helped me the most was:

http://vahana.com/vhdl.htm

Whatever book you start with be sure that it is focuses on synthesis. VHDL started out for simulation so there is a lot of documentation out there that is geared towards simulation. Simulation is good for verifying a design but code written for simulation will not run on a FPGA. It can become very frustrating if you don't understand that from the beginning.

Your VHDL code below looks good, it should work. I would consider removing the pullup resistor statement from the ucf file but besides that it looks good.

Jack.

[Guest AtomSoft]

Thanks a ton Jack, I always like asking about personal recommendations. You are like the 3rd person to recommend that book. So i guess its a good one

Ill be sure to focus on synthesis. Ill remove the resistor since it actually has no use there.

Oh and thanks for the comment on the store. Business is slow but i dont mind. At least i have stock to buy from myself heh...

Thanks again and im off to look into that DCM stuff...

Oh btw, love the videos dude!