C/RAM wing

[alvieboy]

Let's start a new thread for the upcoming C/RAM wing.

Jack: I just received it, and I successfully uploaded the CPLD program using my S3ESK (putting the device in the middle of the JTAG chain). Now, on to testing the CPLD program.

If this goes OK I'll publish the CPLD controller code plus documentation on how to use it, and a 32-bit wishbone controller for papilio.

[Jack Gassett]

Sweet,

I'm looking forward to getting back from California and start hacking on this. I head back home tomorrow.

Jack.

[alvieboy]

Ok, I have good news and bad news.

Good news is that design works as expected, by bitbanging the relevant pins. Despite all the heat

Bad news is it cannot handle my 96MHz clock, and the culprit is the CPLD:

Slack:                  -2.600ns (requirement - data path)

  Source:               state_FSM_FFd3.Q

  Destination:          address<9>.D

  Requirement:          10.400ns

  Data Path Delay:      13.000ns (Levels of Logic = 5)


  Data Path: state_FSM_FFd3.Q to address<9>.D

    Delay type         Delay(ns)  Logical Resource(s)

    ----------------------------  -------------------

    tCOI                  0.500   state_FSM_FFd3.UIM

    tF + tLOGI + tPTA + tSUI  12.500   address<9>.D

    ----------------------------  ---------------------------

tF itself is 8ns.

So Max. freq. for this design is about 77MHz (slightly less). Still I have to confirm timings, additional delay on read might be necessary due to latency (meaning an extra clock cycle on read).

Downgrading to 50MHz/48MHz should be enough for VGA 800x600, with 4 bit per pixel, while leaving room for CPU access.

Are you considering a CoolRunnerII or similar for a next version ? I wonder if we could fit an SDRAM controller in one of these, but they are probably too small.

Alvie

[alvieboy]

Just to clarify: the design being run is not the original, but rather my own which uses an approach similar to that of an SPI ram, but with a 8/13 bit datapath.

roughly this:

This shows a 32-bit write followed by a 32-bit read, 8 bit at the time.

Here's the bitbanging log:

Starting memory test

E: Select TRUE

E: Set bus OUTPUT

E: Set up data 0x00000100

E: Set write to HIGH

E: Clock up

E: Clock low

E: Set up data 0x00000000

E: Clock up

E: Clock low

E: Set up data 0x000000dd

E: Clock up

E: Clock low

E: Set up data 0x000000ff

E: Clock up

E: Clock low

E: Set up data 0x000000bb

E: Clock up

E: Clock low

E: Set up data 0x000000aa

E: Clock up

E: Clock low

E: Set write to LOW

E: Set bus TRISTATE

E: Select FALSE

E: Select TRUE

E: Set bus OUTPUT

E: Set up data 0x00000100

E: Clock up

E: Clock low

E: Set up data 0x00000000

E: Clock up

E: Clock low

E: Set bus TRISTATE

E: Clock up

E: Clock low

E: Read bus returns 000000dd

E: Clock up

E: Clock low

E: Read bus returns 000000ff

E: Clock up

E: Clock low

E: Read bus returns 000000bb

E: Clock up

E: Clock low

E: Read bus returns 000000aa

E: Select FALSE

This is from an actual run on HW, not simulation.

Alvie