Guest Blue12 Posted April 10, 2011 Report Share Posted April 10, 2011 First off thanks to everyone for making this project. It is great. Hello I downloaded the Arduino IDE Papilio-ArduinoIDE0018f. I edited the makefile for simulation like the video recommended and put the FPGA source in the directory pointed to. When I run the compilation of the recommended sketch holding the shift key I get the normal output...it is missing the line that follows these two lines. Merging Verilog Mem file with Xilinx bitstream: ./data2mem -bm bitstreams/AVR8_PapilioOne_bd.bmm -bt bitstreams/AVR8_PapilioOne.bit -bd out.mem -o b out.bit ./data2mem -bm bitstreams/AVR8_PapilioOne_bd.bmm -bt out.bit -d > out.dmp ....there should be the line about simulation here.(so says the video) So I was wondering if anybody has had a similar problem? I am using 32bit vista and Xilinx ISE 13. I don't know if 13 would cause a problem???The posted projects are from 11, and I was prompted to convert them, so I did. The code loads fine onto the board so that is great it is just the simulator that is not working. Any help is appreciated thanks! Link to comment Share on other sites More sharing options...
Jack Gassett Posted April 10, 2011 Report Share Posted April 10, 2011 I'm very sorry that'd something I overlooked. You need to select the custom board type in the arduino ide. I'll work on updating the makefile. Link to comment Share on other sites More sharing options...
Guest Blue12 Posted April 11, 2011 Report Share Posted April 11, 2011 Thanks for the response that was the problem...I did not select custom core in the IDE. This is so awesome...never thought I would actually get to see all of this, it is very cool. Feel free to delete this if this was obvious and I missed something. Thanks for the help. Link to comment Share on other sites More sharing options...
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