Guest jbeale Posted March 3, 2011 Report Share Posted March 3, 2011 I would like to be able to measure time intervals with very high resolution, better than a simple counter which would give me no better than 3 nsec resolution using the fastest possible clock (311 MHz). So I'm wondering about an advanced technique such as the FPGA TDC implementation described here: http://lss.fnal.gov/archive/2009/conf/fermilab-conf-09-275-e.pdf Is it possible to imagine something like this on the Papilio One board, or is this out of the question? I understand that this sort of thing is a current academic research topic, and I'm just a beginner at FPGAs, but I'm curious. Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 4, 2011 Report Share Posted March 4, 2011 Hello, I took a quick look at the paper and it looks like they are just getting really low level with the LUT's that are available with an FPGA. From my brief overview of the document I don't see any reason this would not be possible with the Papilio One. Without really digging into it I can't say for sure, but all the basic elements they are talking about is available in the Spartan 3E that is used on the Papilio One board. Jack. Link to comment Share on other sites More sharing options...
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