Monitor FPGA internals with Open Workbench Logic Sniffer


Guest matthew180

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Guest matthew180

I watched the tutorial on using the Logic Sniffer to monitor FPGA internal state last night, and I was blown away!  Fantastic stuff!  I just got my Logic Sniffer and this is something I can use TODAY!  There is so much you can do with the Xilinx tools, it is overwhelming sometimes.  Tutorials like this one really help in getting things done.

Thanks!

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Hi Jack

We chatted the other night regarding the OLS and i then took a look at your website (new you were a developer with Ian at DP).I too watched the video "Monitor FPGA internals" plus the others  and checked out the rest of the sight.Must say i was so impressed i ordered a Papillo1, a wing  and some other bits.

This should be a great addition to my OLS & buspirate and i look forward to learning to prototype designs  with FPGA's, so the more tutorials you can provide the better.I have a couple of questions:

After the chat between yourself and Ian(dogsbody) the other night regarding the OLS it looks to me like it will soon become a Verilog design  as opposed to VHDL.What would you advise me as someone who is about to learn one or the other which i should pick to start with, my main criteria being the more info/tutorials/help the better. I guess what i really want to know is are you going to start using Verilog with the Papilo or stay with VHDL and is there much difference between the two.

My other question and i am not sure if  i should be asking here but could not find the answer at the shop.On my order it said a couple of the items were on backorder does that mean you will ship what is available now or wait until all the items are  available?

Thanks

Nick

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Nick,

Thanks for the order, the whole order will be shipping out this morning. A couple things were backordered but usually that just means that I have everything I just need to build the item when an order comes in. I usually try to put a notice on the product page if something will take more than a couple of days.

Learning FPGA's is much closer to learning how to design a circuit board than it is to learning a new language like C. Once you get your mind wrapped around a new way of thinking about things it is very rewarding all the amazing things you can do.

I'm releasing a new project today for the Papilio One that provides a fun example of using the VGA Wing with the Papilio One. The goal is to keep releasing practical examples that people can learn from and reuse in their own projects.

As far as the question about learning VHDL or Verilog. I would focus on one in the beginning for sure, I started with VHDL. VHDL seems to be popular in Europe, Universities, and government. Verilog seems to be popular for corporate entities, apparently you can't get a job in silicon valley if you know VHDL, everything is Verilog. In my experience the majority of what I've run into on Opencores and other Open Source sites is VHDL, while stuff from Xilinx is Verilog. I deal with much more VHDL than Verilog so I'm happy that VHDL was what I learned first. Ultimately I think it is good to be functional in both, but it got very confusing when I first started and was trying to learn both. I think the majority of what I'll be doing is going to be in VHDL.

Well, I hope you enjoy messing around with the Papilio One.

Jack.

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Guest matthew180

Nick,

I learned VHDL first, and concur with Jack that ultimately you should be proficient in both.  They are both HDL's and in the end are doing the same thing.  Also, you must make sure you do not think of the HDL as "code" like a programming language.  It does not work that way.  You can get by initially with that thinking, but eventually things will start to break and you will have to back up and rethink what you are doing.

I found that thinking how I would make the circuit with 74ls logic helped a lot.  It also gives you a new understanding of digital circuits and computers, and I'll never look at a datasheet the same way again.  It is pretty fun and very rewarding, but a lot of work too.  It takes time and you have to stick with it, but it is definitely worth the effort!

I also found that there are more examples and available "cores" in VHDL, but that may just be my perception.

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