MyHDL High level Science & Math Python to Verilog doesn't work that way

[Guest josheeg]

MyHDL High level Science & Math Python to Verilog for xilinx schematic modules...

I got this on the myhdl forums "You cannot do what you are asking with MyHDL.  MyHDL is still an RTL.  You can not take arbitrary python and turn it into hardware.  All the tools and libs can be used for simulation but not for synthesizing hardware.

.chris"

I found MyHDL is a python package and with little additions labeling ports higher level functions could be compiled into verilog code.

I am still in the process of seeing how much it can do with the minimal modification and if it can work with higher level math and sci libraries.

Now to take the idea a little further could the doxigen output from generic math and science libraries can their be a script that would make verilog code from all the science and math libraries allowing schematic friendly modules to be created and high level fpga design be semi automated....