Scilab converts matlab control systems simulates system and exports verilog

[Guest josheeg]

So you found some great signal processing code in matlab control system vision processing or multichannel independent component analysis to separate the mixed biopotential signals measured by your analog to digital converter into the unmixed signal and some correlation to the source of the signal.

Now you wonder How do I make that work in parallel in hardware and use open source tools?

Matlab code can be converted using scilab converter into scilab a open source matlab like better thing.  That has a model simulator like simulink. It has a simulator called scicos. Now their is Scicos-hdl that will Automatically generates Description Language(SystemC ,VHDL and Verilog ).

These files can be used as schematic symbols in xilinx software in Linux or played with further in this program or the simulator modeler...

[Jack Gassett]

Wow,

This is a whole area of coolness that I have not even considered exploring before. You have definitely piqued my interest, now when time permits I will start some exploring. I stumbled across a Xilinx App note the other day that talked about using DSP code from Matlab. That might be a good place to start as well.

Jack.

[Guest josheeg]

Scilab & Scicos seem to have split & the scicos-HDL install instructions don't match what script I am supposed to modify to make it work...

So as of right now the complex matlab blind source separation throws I think 3 errors converting the code to scilab.

I tried throwing scicor-HDL in and make some simple function work but no luck the instructions don' t match the newest scilab version or packaging system.

But the code is open source in python also and their are high level math and science functions it that apparently the matlab code has been converted to python. I wonder how different it is after those two libraries math and science are added to python.

So their is MyHDL a python to verilog generator...

This people have used and their are examples and a 100 page manual. That proably don't have to be completely used.

Now you can see if small functions of the python code are made into mini programs they can be tested and compared in hardware and verilog modules can be created open source to have a library of schematic symbols to make the entire system more parallel only in fpga.

I got this from the myhdl forums "You cannot do what you are asking with MyHDL.  MyHDL is still an RTL.  You can not take arbitrary python and turn it into hardware.  All the tools and libs can be used for simulation but not for synthesizing hardware.

.chris"