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Showing results for tags 'wishbone slot'.
I would like to implement a ZPU wishbone slot for an i2s receiver/transmitter using the open core project I2S Interface (http://opencores.org/project,i2s_interface) This opencore I2S component is already implemented as a wishbone peripheral and requires an input signal called "wb_sel_i" / "wishbone input select" which I am not certain how this should be wired up to the 100 bit wishbone input signal on the ZPU. In some projects it is referred to as a 4 bit bus: input [3:0] wbs_sel_i, Where can I find more information about what input and output signals are available from the wishbone bus? Is there a good resource where I can learn about the wishbone protocol? I am using papilio duo. I am fairly new to FPGAs but am learning quickly. Thanks.