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Showing results for tags 'vivado'.
Hi, I'm new to your platform and am interested in using the AVR8 softcore on a Nexys 4 development board that has a Xilinx Artix 7 FPGA programmed using Vivado. I've tried using the AVR Core from Opencores <https://opencores.org/project,avr_core> but first ran into problems with RAMB4_S8 not being supported past the Xilinx 6 series FPGAs. Then I had timing errors at low speeds of 4MHz and with their JTAG implementation. I noticed you've had quite a success with modifying the core for the Papilio line. Will your implementation work with an Artix 7 through the Vivado IDE? What would I need to modify in the VHDL to get it working? I'm specifically interested in using avr-gcc to compile C programs and run them on the AVR8 softcore. Any help would be greatly appreciated. Thank you, Patrick
Hi, I am new to this forum. I am running a course on logic design and I want to include a practical introduction to FPGAs. I am considering Papilio as the platform to use as there will not be time to learn VHDL or Verilog. My students are already used to using schematic design tools such as Proteus. We are using Windows 10. Is Papilio the right solution? I understand that Xilinx have superseded ISE with Vivado (which is more complicated and does not allow schematic entry). How does this affect Papilio and DesignLab? Many thanks.