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  1. Hi. I am new to FPGA design (but an experienced electronics engineer). I am learning how to create simple designs on a Papilio One 500k with ISE schematics. I am familier with basic logic design, and so far I have created some simple combinational logic and a divider chain to produce a 10Hz clock. This works fine, but when after editing and add more bits on, the existing parts no longer function properly. The frustrating thing is that the schematics look correct, but they do not function as expected on the FPGA. After searcing the internet for answers, I suspect it might be something to do with net names or constraints, but that's as far as I have got. Can anyone point me in the right direction (I cannot be the only beginner have these problems!)? By the way, I am aware there are limitations in using schematics (compared with using Verilog or VHDL). I am developing this project for my college students and there will be insufficient time for them to learn an HDL, although I will of course give them an introduction to the subject. Many thanks for reading this.