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hi, i'm using designlab 1.0.8 with ise 14.7 on ubuntu 17.04 amd64, targeting a papilio pro/spartan 6 with the zpuino soft processor. i've got a working proof-of-concept design which combines a few bits and pieces, namely the whirlyfly (whirlygig) random number generator (https://github.com/zdavkeos/whirlyfly), a couple wishbone uart's (COMM_zpuino_wb_UART.vhd), and a wishbone watchdog peripheral written in verilog that i've been trying to integrate (https://github.com/freecores/watchdog/tree/master/rtl/verilog). the rng and uart components appear to be working fine, giving me up to 280KB/s or so of random data when polling both wishbone uart's sequentially at 3mbit/s. i'm then using the reference blake2s hash implementation (https://github.com/mjosaarinen/blake2_mjosref) to further "whiten" the output of the rng's. this slows down the output to about 30KB/s which is fine considering it's a complex operation. that's not the issue. anyhow, the wishbone peripherals included in designlab, as well as the schematic representation of the zpuino 2.0 soft processor bundle the input and output wires into the wishbone_in/wishbone_out connections, which i assume is for simplicity when placing components using the schematic editor in ise. the watchdog.v implementation linked previously is designed with all of the wishbone wires broken out like: module watchdog(wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_int_o); i've been trying unsuccessfully now for a while to modify the watchdog.v to present the same interface, so i can easily attach it to the zpuino using the schematic editor gui (i.e. Papilio_Pro.sch) in ise. without knowing how to modify the schematic symbol after generating it, i just took the one from the wishbone uart included in designlab, replaced the relevant variables and removed the tx/rx, and overwrote the existing watchdog.sym in the project directory. that seemed to work fine and let me drag & drop the watchdog onto an open wishbone port on the zpuino. the issue i'm having is that i can't seem to get the pre-synthesis rtl schematic viewer in planahead to "alias" the slices of wishbone_in/wishbone_out to the friendly-named wires representative of their function within the wishbone bus (e.g. wire [31:0] wb_dat_i; assign wb_dat_i [31:0] = wishbone_in [59:28];). the design does synthesize fine, but i haven't bothered trying to write C code for the zpuino to interface/write with the watchdog peripheral because of the apparent brokenness being shown in planahead. here's a simplification of what i've been doing unsuccessfully to create the "friendly" aliases of wishbone_in/wishbone_out: // original, simplified module watchdog(wb_clk_i, wb_rst_i, wb_dat_i, ...); parameter Tp = 1; input wb_clk_i; input wb_rst_i; input [`WDT_WIDTH - 1:0] wb_dat_i; ... // new, simplified module watchdog(wishbone_in, wishbone_out); parameter Tp = 1; input [100:0] wishbone_in; output [100:0] wishbone_out; wire wb_clk_i = wishbone_in ; wire wb_rst_i = wishbone_in ; wire [31:0] wb_dat_i; assign wb_dat_i [31:0] = wishbone_in [59:28]; ... // mutual code between original & new ... always @(posedge wb_rst_i or posedge wb_clk_i) if (wb_rst_i) begin stb <= #Tp 1'b0; we <= #Tp 1'b0; dat_ir <= #Tp `WDT_WIDTH'h0; end else begin stb <= #Tp wb_stb_i && wb_cyc_i; we <= #Tp wb_we_i; dat_ir <= #Tp wb_dat_i; end ... attached are abridged screenshots of what planahead shows for the unmodified verilog code straight from the aforementioned github repo (top image), and the seemingly broken output from my modified version where i try to bundle up the wires into wishbone_in/wishbone_out. the dat_ir is where wb_dat_i is showing a single wire instead of [31:0]. also attached is the work-in-progress modified watchdog.v. please keep in mind that these are the first lines of vhdl/verilog i've ever written so my knowledge of syntax/terminology is very limited. thanks! watchdog.v