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Found 16 results

  1. Hallo, I have simple problem with the output of signal in the schematic of Xilinx. I've started Xilinx from the simple default Blink file and wand to connect the clk_96Mhz from the ZPUino Soft Processor to D12 of the Pinout. Everything I tried is going to be an error. Can someone explain me how to do this; ore have a good “tutorial” which is using the Papilio. I want to do this in the schematics to understand how to do this.
  2. Hi, I'm working on a project to get a C64 emulator running on the Papilio DUO. I have a working setup using uno2iec program to emulate the disk drive, but this still requires a laptop connected to the board. I found a project named sd2iec, that uses the SD card to load disk images of, but the compiled program is too big to fit on the ATMega32U4 together with a bootloader. So I need a way to program the AVR directly. I Googled for documentation on how to use the bootloader program routine to upload my software as well, but couldn't find any. Is there a way to program the AVR on the Papilio DUO without bootloader via USB using for example avrdude? Kind regards, Paul
  3. Hey all! I'm a graduate student in chemical engineering at UC Berkeley and as a side-project, I'm exploring the possibility of implementing various types of process controllers on FPGAs. My home operating system is Ubuntu and I had a heck of a night scraping together bits and pieces of advice from across the Internet to get Xilinx ISE and Papilio Loader set up and successfully writing bitfiles to the FPGA, so this morning I wrote up a little how-to guide: This is just a starting point, and I hope to provide step-by-step guides to more advanced projects as I learn them. I'm particularly interested in updating the examples in the excellent but venerable Intro to Spartan FPGA eBook to run on the Papilio Duo and whatever other hardware I can get my hands on, and enable a side-by-side comparison of VHDL and Verilog for anyone who's interested in learning both. I'll improve the setup guide by trimming unnecessary steps just as soon as I have the opportunity to do a fresh install on another machine. In the meantime, I'd love feedback! If you're using Ubuntu, let me know these steps are working for you or if you know of comprehensive guides elsewhere.
  4. If I want to use the FTDI Port B of the FPGA USB port as a serial to USB converter connected to a PC, I understand that I have to use signals BD0 (TXD), BD1 (RXD), BD2 (RTS) and BD3 (CTS) mapped to pins 46, 141, 140, 138 of the FPGA (for full hw handshake). Am I correct ? Is there any interference with the normal Papilio Loader programming ? Regards, José Luis.
  5. Hi folks, I wanted to share with you my recently completed Project using the awesome Papilio Duo platform wit the Classic Computing Shield. It's a migration of Grant Searle's brillant work called MULTICOMP, consisting in a flexible FPGA based architecture for implementing old style 8 bit Retro-computers using Z80, 6502 & 6809 "Soft-core" CPU's. Below is the link to the Showcase article on this site. Cheers, José Luis.
  6. Hi, I wonder how the access to the on-board RAM can be implemented and organized. So far I know that a ZPUino uses the on-board RAM to store programs and data. If I understand it correctly, the ZPUino implementation uses the sram_ctl8.vhd source to access the RAM chip via a Wishbone bus interface. I want to use the Papilio DUO to simulate an expansion board for an old 6502-based computer (Ohio Scientific Challenger 1P). On the one hand I want to use a part of the Papilio DUO RAM chip as a memory expansion for the 6502 board. On the other hand a floppy controller with attached floppy disks shall be simulated with storage on an SD card. So for the RAM expansion alone I only need to translate the 6502 bus to something that can communicate with the Papilio DUO's RAM chip. I either could create a Wishbone bus wrapper around the 6502 bus, and use the sram_ctl8.vhd as-is, or I could directly build a bridge from the 6502 bus to the RAM chip based on the internals of the sram_ctl8.vhd source. But when the floppy controller comes into the picture it gets more complicated. I need to simulate some of the chips for the floppy controller (6850 ACIA and 6820 PIA) and map them into the address space of the 6502. For access to an SD card I will either need to use a ZPUino or the real ATmega32U4 processor. With a ZPuino I would need to divide the RAM between the memory expansion and the ZPUino. So lots of questions arise: How can I divide the RAM between the ZPUino and other parts of my design? Could that be managed with compile and link time options when building the sketch for the ZPUino, or would I need to build something in VHDL? Is it even possible at all to influence the ZPUino's use of the RAM chip without modifying its implementation? Would it be better to use the ATmega32U4 for implementing the access to the SD card? I'm obviously at the very beginner level regarding designing and implementing such a project, so I would be very grateful about any tips and experiences in this area. Thanks Stephan
  7. Version 1.0


    The Computing Shield provides all of the hardware needed to recreate computing systems on the Papilio DUO.
  8. rmb


    Hi I would like to communicate with MCP4725 DAC from Papiio DUO through I2C. Is it possible to use I2C library or it could work only with WII Chuck? Thank you rmb.
  9. Hi, I'm very new here so please forgive me if I ask stupid questions. 1 - I recently brought a RetroCade someone was selling on eBay for £68.60 ($106.26 I'm not even sure if I paid a fair price?). Sadly thought the screen is damaged please can someone tell me the cheapest place to buy a new one in the UK (or EU online) and what exactly to buy, could I replace it with a RGB equivalent as the blue light hurts my eyes a bit and it's nice to adjust the colour? 2 - Would the RetroCade work with the Papilio DUO? 3 - I purchased this having read this: I am guessing the since that was posted in 2013 the Mac software will be out by now, where can I download it? SF.
  10. Hi all, I received my Duo last week, and this weekend I've been porting the Acorn Atom FPGA design to run on it. Here's the end result: You can get more details from the thread over at This design currently uses an AVR Soft Processor to run the AtomMMC software stack for the SDCard interface. My next step is to try switching to the ATmega32U4, which will free up quite a lot of FPGA resources. All of the VHDL code is on github: There is also a Duo bit file: If you want to try this out, you'll need the Atom Software Archive. Download from the above thread, unzip it onto a blank FAT32 format MicroSD card, pop in into the Duo and hit Shift-F10 (F10 is mapped to the Atom Break key). Here's a screenshot of the Menu system help page: Search (S) is the single most useful way of finding a specific program, once you know what it's called. GALAXIAN (Bug Byte) is a good program to try first! Please let me know if you manage to get this working, either here, or over on the forums. Dave
  11. Hi, for my project I'm thinking about designing a stackable shield PCB that I can plug into the headers of the Papilio DUO. I looked at Fritzing as a design tool, and it has already a prepared "Arduino Mega Shield PCB". The Papilio DUO Hardware Guide says that the pins of the Papilio DUO are "arranged in a Arduino Mega form factor". Does that mean that I can be confident that the pins of the Papilio DUO match exactly that of an Arduino Mega and that an Arduino Mega stackable shield will fit into the headers of the Papilio DUO? Thanks Stephan
  12. Hi, I'm new to FPGA programming. I'm interested in the Papilio DUO and I have some general technical questions. I have an old 6502-based computer (Ohio Scientific Challenger 1P). The project that I'm thinking of is to build a floppy controller with simulated floppy drives. An SD card would be used to provide the floppy storage. I would also like to implement a 32 kB RAM expansion for the machine. My first question is, would the Papilio DUO be an appropriate platform for this kind of project? The FPGA would need to provide the logic that on the real board was implemented with an 6820 and 6580 chip and additional TTL logic chips. To avoid any confusion, I'm talking here about 1980's technology, where the CPU was clocked with 1 MHz. The second question is, how exactly can the 512 kB or 2 MB RAM of hte Papilio DUO be used? Is the RAM exclusively needed for storing the logical configuration of the FPGA, or could it also be used to store data, and the FPGA makes it look like RAM to the 6502 CPU? Thanks for your time Stephan
  13. Hi, I got my papilio Duo today and tried the tutorials. The first two tutorials worked fine but I got stucked when doing the Editing Circuits Quickstart tutorial. I got an error message that some source files are missing. (see the screenshot below) When ignoring this I get an error message when trying to generate the programming file. Can someone help please? Thanks, paul p.s. I have tried editing another circuit but I always get the following error message when trying to generate the programming file: ERROR:HDLCompiler:410 - "C:.....\cuircuit\DUO_LX9\Papilio_DUO_LX9.vhf" Line 173: Expression has 166 elements ; expected 201
  14. Version 1.0


    The LogicStart Shield provides everything needed to get started with VHDL and FPGA development on the Papilio with one convenient and easy to connect circuit board. Note: The LogicStart Shield requires the Papilio DUO board.
  15. File Name: LogicStart Shield Generic UCF File Submitter: Dhia File Submitted: 06 Feb 2015 File Category: Papilio UCF (User Constraint) Files The LogicStart Shield provides everything needed to get started with VHDL and FPGA development on the Papilio with one convenient and easy to connect circuit board. Note: The LogicStart Shield requires the Papilio DUO board. Click here to download this file
  16. Version 1.0


    The Papilio DUO is a FPGA on the top and Arduino on the bottom. This is the ucf file which maps the FPGA pins for the board.