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Found 3 results

  1. Hello, i've read about fpga project at and then i have been tryring to compile and synthesize the vhdl program by myself. If i checked syntax one by one, there's no problem (no error). But, when i try to synthesize, the result always not successful because there's no syntax in frame buffer module. So, i'm looking for help about how to fix this problem. Then, i also want to know about what is "IP Block Memory Generator" that the project writer's said at hamsterwork. I am using OV7670 camera module and Nexys 4 FPGA Board. And i dont know how to connect OV7670 to nexys 4 board. Please help me, thank you
  2. Hello, I am brand new to FPGAs and am trying to 1) learn about FPGAs and 2) save an image from a camera to an SD Card using FPGAs. The goal is to use this as a stepping stone to develop a stand-alone aerial imaging system for Quadcopters, aircrafts, etc. Thank you for taking the time to read this, and please excuse me for my novice comments. I am having trouble finding a project that goes through the details of writing an image from a camera module much like the ov7670 (link below) to the MicroSD Wing (link below) using a Papillo board. If you know of any projects that are in anyway similar, could you forward them? Also, I am planning on ordering the Papillo One board and a few wings so I can learn by doing. If you have any recommendations on specific hardware that would be beneficial for my goal, I would love your input. ov7670: MicroSD Wing: Just to say it, I am planning on working this project and updating my status to this forum in case anyone else is interested. Open Source all the way. Thank you guys! -CB
  3. NET "clk50" TNM_NET = clk50;TIMESPEC TS_clk50 = PERIOD "clk50" 31.25 ns HIGH 50%;NET "clk50" LOC = "P94"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0NET "OV7670_PWDN" LOC = "P134" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA0NET "OV7670_RESET" LOC = "P133" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA4NET "OV7670_DATA<0>" LOC = "P132" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA1NET "OV7670_DATA<1>" LOC = "P131" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA5NET "OV7670_DATA<2>" LOC = "P127" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA2NET "OV7670_DATA<3>" LOC = "P126" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA6NET "OV7670_DATA<4>" LOC = "P124" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA3NET "OV7670_DATA<5>" LOC = "P123" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA7NET "OV7670_DATA<6>" LOC = "P121" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB0NET "OV7670_DATA<7>" LOC = "P120" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB4NET "OV7670_XCLK" LOC = "P119" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB1NET "OV7670_PCLK" LOC = "P118" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB5NET "OV7670_HREF" LOC = "P117" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB2NET "OV7670_VSYNC" LOC = "P116" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB6NET "OV7670_SIOD" LOC = "P115" | IOSTANDARD=LVTTL | SLEW=SLOW | PULLUP; # JB3NET "OV7670_SIOC" LOC = "P114" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB7NET "OV7670_PCLK" CLOCK_DEDICATED_ROUTE = FALSE;#NET "LED<0>" LOC = "P79" | IOSTANDARD=LVCMOS25 ; #NET "LED<1>" LOC = "P81" | IOSTANDARD=LVCMOS25 ; #NET "LED<2>" LOC = "P83" | IOSTANDARD=LVCMOS25 ; #NET "LED<3>" LOC = "P85" | IOSTANDARD=LVCMOS25 ; #NET "LED<4>" LOC = "P88" | IOSTANDARD=LVCMOS25 ; #NET "LED<5>" LOC = "P93" | IOSTANDARD=LVCMOS25 ; #NET "LED<6>" LOC = "P98" | IOSTANDARD=LVCMOS25 ; #NET "LED<7>" LOC = "P100" | IOSTANDARD=LVCMOS25 ; NET "vgaRed<0>" LOC = "P78";NET "vgaRed<1>" LOC = "P74";NET "vgaRed<2>" LOC = "P95";NET "vgaGreen<0>" LOC = "P84";NET "vgaGreen<1>" LOC = "P82";NET "vgaGreen<2>" LOC = "P80";NET "vgaBlue<1>" LOC = "P92";NET "vgaBlue<2>" LOC = "P87";NET "vgaHSync" LOC = "P97";NET "vgaVSync" LOC = "P99";NET "button" LOC = "P47";Hello. I was inspired by Volkhur's (spelling?) OV7670 project, but I wanted to add the VGA output as an exercise, so I found Hamster's work with the Basys, and based my design entirely on his work. I have made some progress, but I am hitting a roadblock. At first, when I hooked up my TV's VGA port to the VGA port of the Mega Wing, the TV reported "SIGNAL NOT FOUND." I found some errors in my constraints file and fixed those and now the TV reports, "UNABLE TO READ SIGNAL," or something to that effect. I count this as progress, as the TV initially could not even see a signal, and now it sees the signal, but doesn't understand it. Based on the warnings I got when I compiled the source files, I believe it's a PCLK issue. I'm not sure if I can tell you exactly what sort of help I need, but I would appreciate it if you could look at the warning and see if you can help me identify what the possible issue might be. I will go ahead and put my constraints in here, too. I believe this is where the problem originates. This might or might not be important information, but what I did was I connected the Mega Wing to my Pro with male-to-female wires. I directly connected the VGA pins to the same location that it would be connected to on the Pro. I also connected my OV7670 to the Pro with a set of male-to-female wires and located those to the headers where the LEDs and switches normally are on the Pro (Header pin set C0-C15). The PCLK pin of the OV7670 module is physically connected to P118 (C4). The warning I got seems to indicate that this is not ideal.