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Found 3 results

  1. jammasterz

    Generating DCM on Papilio Pro

    Hello! I'm following a tutorial called "Intro to Spartan FPGA" : and I ran into a problem. In chapter 18, we are supposed to generate a DCM. Unfortunately, this tutorial is written for Spartan 3, and all the options that are available under the clocking submenu in the CORE Generator are for Spartan 3. This means that I have no idea how to create a DCM on Spartan 6. I tried looking for answers on the internet, but the answers were far too technical and I didn't understand much of the content. I was specifically trying to run this code, written by Hamster: but it requires DCMs. Why he would need 2 of those is a whole new problem that i will try to take on when I actually get one of them working. Maybe you know how to solve this problem?
  2. Hey there. I'm following this tutorial: (By the way there is no code in the repository, only the book itself); I'm currently on chapter 13 and I'm having problems with getting it to work. I'm supposed to: • Create a new module - a 30-bit counter called "counter30", with the following external signals:– clk : in STD_LOGIC– enable : in STD_LOGIC– count : out STD_LOGIC_VECTOR(29 downto 0) • View the ’Instantiation Template’ for your component. Copy the component declaration into your switches_leds.vhd source• In switches_leds create an instance of counter30– Connect the counter’s count output to a bus called count1– Connect the "enable" signal to switch(0)– Connect the clock– Connect the top four bits of count1 to LEDs(3 downto 0). I've spent a ton of time trying to figure out whats wrong but I have no idea. This is what I have so far:The counter30 module:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter30 is Port ( clk : in STD_LOGIC; enable : in STD_LOGIC; count : out STD_LOGIC_VECTOR (29 downto 0));end counter30;architecture Behavioral of counter30 is signal counter : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');begin clk_proc: process(clk) begin if enable = '1' then if rising_edge(clk) then counter <= counter + 1; end if; end if; end process;end Behavioral;The main program: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity Swiches_LEDs is Port ( switches : in STD_LOGIC_VECTOR(7 downto 0); LEDs : out STD_LOGIC_VECTOR(3 downto 0); clk1 : in STD_LOGIC);end Swiches_LEDs;architecture Behavioral of Swiches_LEDs is COMPONENT counter30 PORT( clk : IN std_logic; enable : IN std_logic; count : OUT std_logic_vector(29 downto 0) ); END COMPONENT; signal count1 : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');begin Inst_counter30: counter30 PORT MAP( clk => clk1, enable => switches(0), count => count1 ); LEDs(3 downto 0) <= count1(29 downto 26);end Behavioral;Does anybody know whats wrong?
  3. Hey there. I hope this is the right tab for this type of question. I just got my Papilio Pro V1.3 along with LogicStart wing V1.2. This is the very first time I play with a FPGA. I follow a tutorial in which I'm told to upload this program: library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity Swiches_LEDs is Port ( switch_0 : in STD_LOGIC; switch_1 : in STD_LOGIC; LED_0 : out STD_LOGIC; LED_1 : out STD_LOGIC);end Swiches_LEDs;architecture Behavioral of Swiches_LEDs isbegin LED_0 <= switch_0; LED_1 <= switch_1;end Behavioral; Pretty basic. Then I created a constraint file, that I modified a little so that the pin numbers are correct for Papilio Pro (tutorial is written for One): # Constraints for Papilio Pro NET switch_1 LOC = "P120" | IOSTANDARD=LVTTL; NET switch_0 LOC = "P121" | IOSTANDARD=LVTTL; NET LED_1 LOC = "P133" | IOSTANDARD=LVTTL; NET LED_0 LOC = "P134" | IOSTANDARD=LVTTL;Then I find the bin file and launch it(yes I have papilio loader installed with all the drivers). I see that the RX and TX diodes are blinking(for about a minute or 2). But then the program doesn't work. The switches don't affect the LEDs at all, and there are some random LEDs that are blinking, and sometimes 2 segments from the built in 7seg blink along with the diodes. I have no idea what I've done wrong.