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Showing results for tags 'lanai'.
I was updating my LLVM tree today (long time since I did it) to prepare for XThunderCore SmallISA, and I found a new CPU in there, called "Lanai". A quick search returned some info - this CPU seems to be in development by Google , and it's similar to a microcontroller but aimed at massive parallel computations. Did not have time to explore much - looks like a classical RISC to me ythough. You can get a glimpse of the instruction formats by looking at the LLVM implementation: https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Lanai/LanaiInstrFormats.td Any of you ever heard of this, and if any soft-core implementation is available in the wild ? Magnus ? (I will update you guys regarding the XThunderCore SmallISA in a couple of weeks). Alvie  https://www.phoronix.com/scan.php?page=news_item&px=Google-Lanai-Architecture  http://www.theregister.co.uk/2016/02/09/google_processor/  http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html