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Found 8 results

  1. hi, i'm using designlab 1.0.8 with ise 14.7 on ubuntu 17.04 amd64, targeting a papilio pro/spartan 6 with the zpuino soft processor. i've got a working proof-of-concept design which combines a few bits and pieces, namely the whirlyfly (whirlygig) random number generator (, a couple wishbone uart's (COMM_zpuino_wb_UART.vhd), and a wishbone watchdog peripheral written in verilog that i've been trying to integrate ( the rng and uart components appear to be working fine, giving me up to 280KB/s or so of random data when polling both wishbone uart's sequentially at 3mbit/s. i'm then using the reference blake2s hash implementation ( to further "whiten" the output of the rng's. this slows down the output to about 30KB/s which is fine considering it's a complex operation. that's not the issue. anyhow, the wishbone peripherals included in designlab, as well as the schematic representation of the zpuino 2.0 soft processor bundle the input and output wires into the wishbone_in/wishbone_out connections, which i assume is for simplicity when placing components using the schematic editor in ise. the watchdog.v implementation linked previously is designed with all of the wishbone wires broken out like: module watchdog(wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_int_o); i've been trying unsuccessfully now for a while to modify the watchdog.v to present the same interface, so i can easily attach it to the zpuino using the schematic editor gui (i.e. Papilio_Pro.sch) in ise. without knowing how to modify the schematic symbol after generating it, i just took the one from the wishbone uart included in designlab, replaced the relevant variables and removed the tx/rx, and overwrote the existing watchdog.sym in the project directory. that seemed to work fine and let me drag & drop the watchdog onto an open wishbone port on the zpuino. the issue i'm having is that i can't seem to get the pre-synthesis rtl schematic viewer in planahead to "alias" the slices of wishbone_in/wishbone_out to the friendly-named wires representative of their function within the wishbone bus (e.g. wire [31:0] wb_dat_i; assign wb_dat_i [31:0] = wishbone_in [59:28];). the design does synthesize fine, but i haven't bothered trying to write C code for the zpuino to interface/write with the watchdog peripheral because of the apparent brokenness being shown in planahead. here's a simplification of what i've been doing unsuccessfully to create the "friendly" aliases of wishbone_in/wishbone_out: // original, simplified module watchdog(wb_clk_i, wb_rst_i, wb_dat_i, ...); parameter Tp = 1; input wb_clk_i; input wb_rst_i; input [`WDT_WIDTH - 1:0] wb_dat_i; ... // new, simplified module watchdog(wishbone_in, wishbone_out); parameter Tp = 1; input [100:0] wishbone_in; output [100:0] wishbone_out; wire wb_clk_i = wishbone_in [61]; wire wb_rst_i = wishbone_in [60]; wire [31:0] wb_dat_i; assign wb_dat_i [31:0] = wishbone_in [59:28]; ... // mutual code between original & new ... always @(posedge wb_rst_i or posedge wb_clk_i) if (wb_rst_i) begin stb <= #Tp 1'b0; we <= #Tp 1'b0; dat_ir <= #Tp `WDT_WIDTH'h0; end else begin stb <= #Tp wb_stb_i && wb_cyc_i; we <= #Tp wb_we_i; dat_ir <= #Tp wb_dat_i; end ... attached are abridged screenshots of what planahead shows for the unmodified verilog code straight from the aforementioned github repo (top image), and the seemingly broken output from my modified version where i try to bundle up the wires into wishbone_in/wishbone_out. the dat_ir is where wb_dat_i is showing a single wire instead of [31:0]. also attached is the work-in-progress modified watchdog.v. please keep in mind that these are the first lines of vhdl/verilog i've ever written so my knowledge of syntax/terminology is very limited. thanks! watchdog.v
  2. Hi. I am new to FPGA design (but an experienced electronics engineer). I am learning how to create simple designs on a Papilio One 500k with ISE schematics. I am familier with basic logic design, and so far I have created some simple combinational logic and a divider chain to produce a 10Hz clock. This works fine, but when after editing and add more bits on, the existing parts no longer function properly. The frustrating thing is that the schematics look correct, but they do not function as expected on the FPGA. After searcing the internet for answers, I suspect it might be something to do with net names or constraints, but that's as far as I have got. Can anyone point me in the right direction (I cannot be the only beginner have these problems!)? By the way, I am aware there are limitations in using schematics (compared with using Verilog or VHDL). I am developing this project for my college students and there will be insufficient time for them to learn an HDL, although I will of course give them an introduction to the subject. Many thanks for reading this.
  3. Hi, I am new to this forum. I am running a course on logic design and I want to include a practical introduction to FPGAs. I am considering Papilio as the platform to use as there will not be time to learn VHDL or Verilog. My students are already used to using schematic design tools such as Proteus. We are using Windows 10. Is Papilio the right solution? I understand that Xilinx have superseded ISE with Vivado (which is more complicated and does not allow schematic entry). How does this affect Papilio and DesignLab? Many thanks.
  4. After finding the software i needed to make use of the design lab, i've encountered some obstacles. It's asking me to fill out company related info.
  5. Hi, Although all papilio-Dues have the same hardware, I am very curious to know why papilio-due's ability to be programmed in xilinx impact (using digilent plugin) is marked as an unsupported feature that works for some board on may not works for some others? regards.
  6. Hi, I'm workingt on getting started with the DesignLab and ISE workflow, and for that I'm trying to build a simple project without ZPUino. I created a new DesignLab project, edited the circuit in ISE, deleted the ZPUino and everything else from the schematic. I then built a minimal circuit with a clk_divider_30to1hz symbol from the Papilio libraries. I can create a bit file, upload it to the Papilio DUO, and after connecting two LEDs to the configured pins I have two LEDs flashing at 1 Hz and 8 Hz as expected. As a next step I'm trying to run the circuit in the ISim simulator, and I haven't been able to make that work yet. I created a new VHDL test bench, and I added a process for the CLK signal. When I'm starting the simulation, the following warnings appear when the simulation is built: WARNING:HDLCompiler:89 - "C:/Users/stm/Documents/DesignLab/divider/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 68: <clk_divider_30to1hz> remains a black-box since it has no binding entity.WARNING:Simulator:648 - "C:/Users/stm/Documents/DesignLab/divider/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 68. Instance clk_divider_30to1hz is unbound In the wave window the two outputs from the clk_divider_30to1hz symbol appear with an "U" in the "Value" column (see attached screen shot). If I understand it correctly, this means that the two outputs are uninitialzed. Is there any additional configuration necessary in order to run a ISim simulation for a DesignLab project that uses symbols from the Papilio libraries? My test project is also available via DropBox if someone is interested: ThanksStephan
  7. I'm using Xilinx ISE 14.7 to program a Papilio One 250k. I'm trying to simulate a process that uses a BUFG component, and the output of the component is all 0 -- it doesn't follow the input. Here's a small snippet of code: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;entity UART is Port ( CLK : in std_logic; -- CLK runs at 32 MHz CLKDIV : in unsigned(15 downto 0); -- divide to bit clock );end UART;architecture Behavioral of UART is signal BITCLK : std_logic := '0'; -- four clocks per bit signal PREBITCLK : std_logic := '0'; component BUFG port( I : in std_logic; O : out std_logic ); end component;begin Bitclk_Bufg: BUFG port map( I => PREBITCLK, O => BITCLK ); Clk_Proc: process(CLK, CLKDIV) variable PREVDIV : unsigned(15 downto 0) := to_unsigned(0, 16); variable CURCNT : unsigned(15 downto 0) := to_unsigned(0, 16); begin if rising_edge(CLK) then if not (PREVDIV = CLKDIV) then CURCNT := to_unsigned(0, 16); PREVDIV := CLKDIV; elsif CURCNT = PREVDIV then CURCNT := to_unsigned(0, 16); PREBITCLK <= not PREBITCLK; else CURCNT := CURCNT + 1; end if; end if; end process;...I see CLK coming in in my simulation, and I see PREBITCLK being generated. However, the BITCLK output is just 0 no matter how long I run the simulation. Why is this? Isn't it supposed to just buffer the clock, and thus repeat the input? How can I make it do that?
  8. Version 1.0


    Build your own custom ZPUino System on Chip design using the Schematic editor! Just drag and drop the wishbone peripherals you want to design a ZPUino Soft Processor with exactly what you want and then program it with the ZAP IDE. Note: This works under Linux but there are bugs with the schematic editor that give mixed results.