Search the Community

Showing results for tags 'clock'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Community
    • Gadget Factory Reboot 2022
    • Gadget Factory
    • Documentation
    • FPGA Discussions
    • Community Projects
  • Soft Processors
    • Migen/LiteX/Risc-V
    • ZPUino
    • J1 Forth
    • AVR8 Soft Processor
  • Electronics
    • Modules
  • Papilio Platform (Retired)
    • Papilio General Discussion
    • Papilio Pro
    • Papilio One
    • Papilio DUO
    • Papilio Wings
    • DesignLab IDE
    • DesignLab Libraries
    • RetroCade Synth
    • Papilio Arcade
    • Papilio Loader Application
    • Papilio Logic Sniffer
    • Pipistrello
    • Retired
  • Open Bench (Retired)
    • Open Bench Logic Sniffer at Dangerous Prototypes
    • OpenBench Logic Sniffer at Gadget Factory
  • GadgetBox Universal IoT Hardware (Retired)
    • GadgetBox General Discussion
  • Gadget Factory Internal Category


  • Papilio Platform
    • Papilio One
    • Papilio Plus
    • Papilio Wings
    • LogicStart MegaWing
    • ZPUino
    • Papilio Pro
  • Papilio Arcade
  • RetroCade Synth
  • Logic Sniffer
  • FPGAs
  • DesignLab
    • Example Projects
    • Libraries


  • Papilio FPGA
    • Papilio UCF (User Constraint) Files
    • Papilio Bit Files
  • Papilio Arcade
  • RetroCade Synth
  • General
  • Beta (Test) Releases
  • Books

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 3 results

  1. HELLO all, just started my papilio journey and I need to reduce the 32MHz internal clock down to just 5Hz. I tried reading materials about the CMT (clock management tile) but just got more confused. thank u Mar
  2. Hi, I may have not dug enough into the Papilo FPGA cards documentation yet, so I am asking here: What about removing the clock? to work in asynchronous mode. How difficult is this with the different cards (I am yet considering buying the Papilio Pro, but answers for the other cards are also welcomed). Does anyone already did it? For information, I am trying to reproduce some results of Dr. David Rosin from Duke University / Technische üniversität Berlin (, so I really need this asynchronous mode. And I would not go for proprietary devices Best, Julien
  3. My second newbie question, hopefully someone can help me and I'll be forever grateful. I'm using my recently purchased Papilio one 500k to create a 24MHz clock output to feed into a different chip/module. Why am I doing this? Because I bought the wrong oscillator for my other module and I thought hooking it up on the fpga would a quick temp solution. The design is super simple, just the regular 32Mhz clk in, to a DCM which modulate to 24Mhz, then to ODDR2 which drives an OBUF on one of the IO pins. The output pin is set as LVCMOS33 in my ucf and the OBUF driving it is also LVCMOS33 standard. However, when I measure the output on the board with an oscilloscope, the waveforms are really distorted but correct frequency. As if there's too much parasitic cap on the output. Going down to a much smaller freq around 8Mhz the waveforms are much more square. I've calibrated my probes over and over again. Are the "wings" or headers on the Papilio bad for driving such signal? Or do I need to change some iostandard or drive strength? Any advice suggestion? Thanks