Search the Community

Showing results for tags 'VGA'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Community
    • Gadget Factory Reboot 2022
    • Gadget Factory
    • Documentation
    • FPGA Discussions
    • Community Projects
  • Soft Processors
    • Migen/LiteX/Risc-V
    • ZPUino
    • J1 Forth
    • AVR8 Soft Processor
  • Electronics
    • Modules
  • Papilio Platform (Retired)
    • Papilio General Discussion
    • Papilio Pro
    • Papilio One
    • Papilio DUO
    • Papilio Wings
    • DesignLab IDE
    • DesignLab Libraries
    • RetroCade Synth
    • Papilio Arcade
    • Papilio Loader Application
    • Papilio Logic Sniffer
    • Pipistrello
    • Retired
  • Open Bench (Retired)
    • Open Bench Logic Sniffer at Dangerous Prototypes
    • OpenBench Logic Sniffer at Gadget Factory
  • GadgetBox Universal IoT Hardware (Retired)
    • GadgetBox General Discussion
  • Gadget Factory Internal Category


  • Papilio Platform
    • Papilio One
    • Papilio Plus
    • Papilio Wings
    • LogicStart MegaWing
    • ZPUino
    • Papilio Pro
  • Papilio Arcade
  • RetroCade Synth
  • Logic Sniffer
  • FPGAs
  • DesignLab
    • Example Projects
    • Libraries


  • Papilio FPGA
    • Papilio UCF (User Constraint) Files
    • Papilio Bit Files
  • Papilio Arcade
  • RetroCade Synth
  • General
  • Beta (Test) Releases
  • Books

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 9 results

  1. Last night I ported my unfinished MC6847 emulator Verilog code from a Altera EPC4 board to my Papilio One. I have the small VGA wing, which has: hsync; vsync; and 2 bits each for R, G and B. When I found the schematic I was surprised to see that both resistors were the same value, which I believe will only allow my 3 levels of luminance for each colour, so only 27 colours in total. Why not use two different values for the resistors, similar to the scheme used on the other MegaWings? To be honest it isn't an issue for this particular project. I know that I could replace one of the resistors, but I am unable to work with that tiny size of SMD resistor.
  2. I think I'm going insane. I have a Papilio Pro + LogicStart MegaWing. I'm displaying a VGA image by using both (108 MHz, 1280 * 1024 * 60 Hz). So far so good. OK, now I disconnect the LogicStart MegaWing and I manually connect the pins relevant for VGA between the Papilio and the wing by using jumper wires . My VGA display says no signal. I've checked the wiring more times than I can remember. WTF? As a sanity check I tried connecting the relevant wires for a 7-segment display segment (1 segment + 1 anode + GND) and it worked. No luck so far with VGA though... Can anyone reproduce this issue? Which pins did you connect?
  3. Hello, In the Arcade MegaWing schematic each VGA color component has two diodes and one capacitor. Could anyone clarify the following? 1) what are the values of these diodes and capacitors? the schematic doesn't say, it has only a "BAV199" marking 2) In the image <> I see empty soldering pads near the VGA connector, so I guess the diodes and capacitors were not actually installed on production boards, were they? I guess they are not essential, since the LogicStart MegaWing doesn't have them. 3) Essential or not, what is the purpose of that part of the circuit? Thanks a lot!
  4. I have the J1 CPU running on the Papilio Duo. It runs a standard 32-bit ANS Forth, communication is through the UART. It is working quite well; in fact I used it to run my slides for a presentation last week (slides were on microSD, buttons and VGA output from the Computing Shield). Is anyone interested in giving it a tryout? Let me know if so and I will put together a release. Thanks! J.
  5. Hi, I am new to the papilio enviro and to FPGA's ... (still expecting the 1st delivery) In good preparation of my plans with this device I studied alot opn the subject for a few weeks now and and read around in the existing forums. I started messing with VHDL in xilinx ISE .. The concept of FPGA's has attracted me much, but off course there is a lot to learn still .. I was wondering if it would be possible to used these wonderful 8 megs of SDRAM as video memory for VGA output .. ? If yes ... is it then possible to spilt it up and use the leftover as system RAM for some processor soft core (i was thinking of the 65816 because i have a past in that family) ? Or even better like putting it all in one flat address map where the soft core processor can manipulate the video memory direct random adressable ? I understand that access is limited by time slots .. but in burst modes you can do bulk transfers at high speeds .. but there must be alignment with read and write actions between the constant data refresh cycles ... I have seen the modules for testing the sdram .. but diving into that project in ISE is not a good start for beginners maybe since i did not really find a clear interface how to talk to the SDRAM controller module and translating it somehow into a flat always accesible way like the way you use SRAM.... Are there any experts who can elaborate a little more on this ? Grx.. Eric
  6. hello boys, i saw an announce recently about the opensourcing of a 2D/3D commercial GPU of the late nineties: maybe it's good companion for the "soon to come" HDMI wing for Papilio Pro? (or for Pipistrello) bests Andrea PS sadly enough it's in verilog, the "perl" of HDL! :-)
  7. NET "clk50" TNM_NET = clk50;TIMESPEC TS_clk50 = PERIOD "clk50" 31.25 ns HIGH 50%;NET "clk50" LOC = "P94"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0NET "OV7670_PWDN" LOC = "P134" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA0NET "OV7670_RESET" LOC = "P133" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA4NET "OV7670_DATA<0>" LOC = "P132" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA1NET "OV7670_DATA<1>" LOC = "P131" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA5NET "OV7670_DATA<2>" LOC = "P127" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA2NET "OV7670_DATA<3>" LOC = "P126" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA6NET "OV7670_DATA<4>" LOC = "P124" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA3NET "OV7670_DATA<5>" LOC = "P123" | IOSTANDARD=LVTTL | SLEW=SLOW; # JA7NET "OV7670_DATA<6>" LOC = "P121" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB0NET "OV7670_DATA<7>" LOC = "P120" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB4NET "OV7670_XCLK" LOC = "P119" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB1NET "OV7670_PCLK" LOC = "P118" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB5NET "OV7670_HREF" LOC = "P117" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB2NET "OV7670_VSYNC" LOC = "P116" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB6NET "OV7670_SIOD" LOC = "P115" | IOSTANDARD=LVTTL | SLEW=SLOW | PULLUP; # JB3NET "OV7670_SIOC" LOC = "P114" | IOSTANDARD=LVTTL | SLEW=SLOW; # JB7NET "OV7670_PCLK" CLOCK_DEDICATED_ROUTE = FALSE;#NET "LED<0>" LOC = "P79" | IOSTANDARD=LVCMOS25 ; #NET "LED<1>" LOC = "P81" | IOSTANDARD=LVCMOS25 ; #NET "LED<2>" LOC = "P83" | IOSTANDARD=LVCMOS25 ; #NET "LED<3>" LOC = "P85" | IOSTANDARD=LVCMOS25 ; #NET "LED<4>" LOC = "P88" | IOSTANDARD=LVCMOS25 ; #NET "LED<5>" LOC = "P93" | IOSTANDARD=LVCMOS25 ; #NET "LED<6>" LOC = "P98" | IOSTANDARD=LVCMOS25 ; #NET "LED<7>" LOC = "P100" | IOSTANDARD=LVCMOS25 ; NET "vgaRed<0>" LOC = "P78";NET "vgaRed<1>" LOC = "P74";NET "vgaRed<2>" LOC = "P95";NET "vgaGreen<0>" LOC = "P84";NET "vgaGreen<1>" LOC = "P82";NET "vgaGreen<2>" LOC = "P80";NET "vgaBlue<1>" LOC = "P92";NET "vgaBlue<2>" LOC = "P87";NET "vgaHSync" LOC = "P97";NET "vgaVSync" LOC = "P99";NET "button" LOC = "P47";Hello. I was inspired by Volkhur's (spelling?) OV7670 project, but I wanted to add the VGA output as an exercise, so I found Hamster's work with the Basys, and based my design entirely on his work. I have made some progress, but I am hitting a roadblock. At first, when I hooked up my TV's VGA port to the VGA port of the Mega Wing, the TV reported "SIGNAL NOT FOUND." I found some errors in my constraints file and fixed those and now the TV reports, "UNABLE TO READ SIGNAL," or something to that effect. I count this as progress, as the TV initially could not even see a signal, and now it sees the signal, but doesn't understand it. Based on the warnings I got when I compiled the source files, I believe it's a PCLK issue. I'm not sure if I can tell you exactly what sort of help I need, but I would appreciate it if you could look at the warning and see if you can help me identify what the possible issue might be. I will go ahead and put my constraints in here, too. I believe this is where the problem originates. This might or might not be important information, but what I did was I connected the Mega Wing to my Pro with male-to-female wires. I directly connected the VGA pins to the same location that it would be connected to on the Pro. I also connected my OV7670 to the Pro with a set of male-to-female wires and located those to the headers where the LEDs and switches normally are on the Pro (Header pin set C0-C15). The PCLK pin of the OV7670 module is physically connected to P118 (C4). The warning I got seems to indicate that this is not ideal.
  8. Hey guys, I am working on a project to display realtime signal as a plot on the VGA display using Papilio One 500k board with the help of Logicstart Megawing. I'm able to display text message on VGA but it is difficult for me to display a real time signal. It would be very helpful if any of you guys could help me with the logic/program to overcome this difficulty. With regards, Tom
  9. Hello, Which app to use to save PNG file and then convert it with png2zpuinohqvga tool to get correct image ? Given example works, but not my own (getting random colors). I can't find information about image size and colors count, too. Thanks