Search the Community

Showing results for tags 'ISim'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Community
    • Gadget Factory Reboot 2022
    • Gadget Factory
    • Documentation
    • FPGA Discussions
    • Community Projects
  • Soft Processors
    • Migen/LiteX/Risc-V
    • ZPUino
    • J1 Forth
    • AVR8 Soft Processor
  • Electronics
    • Modules
  • Papilio Platform (Retired)
    • Papilio General Discussion
    • Papilio Pro
    • Papilio One
    • Papilio DUO
    • Papilio Wings
    • DesignLab IDE
    • DesignLab Libraries
    • RetroCade Synth
    • Papilio Arcade
    • Papilio Loader Application
    • Papilio Logic Sniffer
    • Pipistrello
    • Retired
  • Open Bench (Retired)
    • Open Bench Logic Sniffer at Dangerous Prototypes
    • OpenBench Logic Sniffer at Gadget Factory
  • GadgetBox Universal IoT Hardware (Retired)
    • GadgetBox General Discussion
  • Gadget Factory Internal Category


  • Papilio Platform
    • Papilio One
    • Papilio Plus
    • Papilio Wings
    • LogicStart MegaWing
    • ZPUino
    • Papilio Pro
  • Papilio Arcade
  • RetroCade Synth
  • Logic Sniffer
  • FPGAs
  • DesignLab
    • Example Projects
    • Libraries


  • Papilio FPGA
    • Papilio UCF (User Constraint) Files
    • Papilio Bit Files
  • Papilio Arcade
  • RetroCade Synth
  • General
  • Beta (Test) Releases
  • Books

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 1 result

  1. Hi, I'm workingt on getting started with the DesignLab and ISE workflow, and for that I'm trying to build a simple project without ZPUino. I created a new DesignLab project, edited the circuit in ISE, deleted the ZPUino and everything else from the schematic. I then built a minimal circuit with a clk_divider_30to1hz symbol from the Papilio libraries. I can create a bit file, upload it to the Papilio DUO, and after connecting two LEDs to the configured pins I have two LEDs flashing at 1 Hz and 8 Hz as expected. As a next step I'm trying to run the circuit in the ISim simulator, and I haven't been able to make that work yet. I created a new VHDL test bench, and I added a process for the CLK signal. When I'm starting the simulation, the following warnings appear when the simulation is built: WARNING:HDLCompiler:89 - "C:/Users/stm/Documents/DesignLab/divider/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 68: <clk_divider_30to1hz> remains a black-box since it has no binding entity.WARNING:Simulator:648 - "C:/Users/stm/Documents/DesignLab/divider/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 68. Instance clk_divider_30to1hz is unbound In the wave window the two outputs from the clk_divider_30to1hz symbol appear with an "U" in the "Value" column (see attached screen shot). If I understand it correctly, this means that the two outputs are uninitialzed. Is there any additional configuration necessary in order to run a ISim simulation for a DesignLab project that uses symbols from the Papilio libraries? My test project is also available via DropBox if someone is interested: ThanksStephan