Search the Community

Showing results for tags 'CPU'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Community
    • Gadget Factory Reboot 2022
    • Gadget Factory
    • Documentation
    • FPGA Discussions
    • Community Projects
  • Soft Processors
    • Migen/LiteX/Risc-V
    • ZPUino
    • J1 Forth
    • AVR8 Soft Processor
  • Electronics
    • Modules
  • Papilio Platform (Retired)
    • Papilio General Discussion
    • Papilio Pro
    • Papilio One
    • Papilio DUO
    • Papilio Wings
    • DesignLab IDE
    • DesignLab Libraries
    • RetroCade Synth
    • Papilio Arcade
    • Papilio Loader Application
    • Papilio Logic Sniffer
    • Pipistrello
    • Retired
  • Open Bench (Retired)
    • Open Bench Logic Sniffer at Dangerous Prototypes
    • OpenBench Logic Sniffer at Gadget Factory
  • GadgetBox Universal IoT Hardware (Retired)
    • GadgetBox General Discussion
  • Gadget Factory Internal Category


  • Papilio Platform
    • Papilio One
    • Papilio Plus
    • Papilio Wings
    • LogicStart MegaWing
    • ZPUino
    • Papilio Pro
  • Papilio Arcade
  • RetroCade Synth
  • Logic Sniffer
  • FPGAs
  • DesignLab
    • Example Projects
    • Libraries


  • Papilio FPGA
    • Papilio UCF (User Constraint) Files
    • Papilio Bit Files
  • Papilio Arcade
  • RetroCade Synth
  • General
  • Beta (Test) Releases
  • Books

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 3 results

  1. Hey guys, I am developing a new CPU (for fun and beyond), which aims to replace the slow ZPU we have been using so far. The new CPU design is coming along very well, and should match and eventually outperform the Xilinx Microblaze in program size, performance (MHz) and implementation size (well, perhaps this one not, let's see). The CPU is 32-bit, RISC-like, with 31 general purpose registers, a zero register, and a few special registers. It's an hybrid of well known CPUs, like Microblaze, ARM, SPARC, and others. All instructions are 16-bit, and can be extended for immediate values. It has 2 to 5 asymmetric ALU, which in certain scenarios allows the CPU to execute two (or more) instructions at the same time. All normal addressing modes are supported. The design uses 3 to 6 pipeline stages, depending on configuration. All branch instructions have delay slots. The objective is to have a fast CPU (something between 100MHz and 166Mhz) , superscalar, and have it fit nicely on a PPro/Papilio One while using the same Wishbone interface as ZPUino does. The current state is: it works in simulation, an assembler/linker is already working, still missing the C/C++ compiler (LLVM), Now... I really need to name it. And this is where I need your advice and help. The best name I found so far is "XThunderCore", or abbreviated, "XTC". What are your ideas ? Can you come up with a better name for it ? Best, Alvie
  2. I was updating my LLVM tree today (long time since I did it) to prepare for XThunderCore SmallISA, and I found a new CPU in there, called "Lanai". A quick search returned some info - this CPU seems to be in development by Google [1][2][3], and it's similar to a microcontroller but aimed at massive parallel computations. Did not have time to explore much - looks like a classical RISC to me ythough. You can get a glimpse of the instruction formats by looking at the LLVM implementation: Any of you ever heard of this, and if any soft-core implementation is available in the wild ? Magnus ? (I will update you guys regarding the XThunderCore SmallISA in a couple of weeks). Alvie [1] [2] [3]
  3. Hi everyone, I just ordered my first Papillio FPGA ! I am continuing a (huge) project that I started based on the Cyclone V GX starter kit from Terassic. I had a hard time finding documentation and support online and decided to move to Papillio. As a Computer Science Engineering student at EPFL (Switzerland), I have had numerous courses that cover various aspects of computer science/engineering. All those courses felt separated. I decided that I wanted to "fill the gaps" in my knowledge of computers. The ultimate goal is to create a tutorial / source code where one can learn practical computer engineering (I'll include links to good theory books/tutorials/articles). I want to cover the following aspects of computer science: - How the hardware works. (Simple multi/cycle multi-core CPU, no caches), VGA, Serial, keyboard, other peripherals (leds ect). - How assembly works - How a compiler works, C-like language design - How a kernel works - How to internet works, either using a computer as proxy (through UART) or if I can find an opensource Ethernet implementation directly from the FPGA. - Writing a simple web-server - Writing some basic javascript The idea is to have for each section: - Some background information - Links to deper / more complex issues (eg: caches, complex theory) - A guided practical "let's do it" I think this covers most of what one needs to know (if you add calculus ) to become a computer scientist. If anyone is interested in the project, I'd be more than happy to do work together ! I currently have: - An assembler / begining of compiler written in F# (I target mono) giving the oportunity to learn functional programming. - - Some VHDL for my CPU. You can find me online: