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About terryphi

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  1. terryphi

    ADC Pinout

    Sorry, nevermind, found it on this webpage: http://papilio.cc/index.php?n=Papilio.LogicStartMegaWing Name Direction Function Arduino Pin Papilio Wing Pin Papilio One Pin Papilio Pro Pin CLK Output Clock 15 A15, AH7 P86 P100 MOSI Output Master Out Slave In 14 A14, AH6 P84 P98 MISO Input Master In Slave Out 13 A13, AH5 P79 P93 CS Output Chip Select (Active Low) 12 A12, AH4 P70 P88
  2. terryphi

    ADC Pinout

    Hello, I'm using a papilio one 500k and a logic-start mega wing. I'm looking at the generic UCF file: # UCF file for the Papilio One 500K board# Generated by pin_converter, written by Kevin Lindsey# https://github.com/thelonious/papilio_pins/tree/development/pin_converter# Main board wing pin [] to FPGA pin Pxx map# -------C------- -------B------- -------A-------# [GND] [C00] P91 [GND] [B00] P85 P86 [A15]# [2V5] [C01] P92 [2V5] [B01] P83 P84 [A14]# [3V3] [C02] P94 [3V3] [B02] P78 P79 [A13]# [5V0] [C03] P95 [5V0] [B03] P71 P70 [A12]# [C04] P98 [B04] P68 P67 [A11] [5V0]# [C05] P2 [B05] P66 P65 [A10] [3V3]# [C06] P3 [B06] P63 P62 [A09] [2V5]# [C07] P4 [B07] P61 P60 [A08] [GND]# [GND] [C08] P5 [GND] [B08] P58 P57 [A07]# [2V5] [C09] P9 [2V5] [B09] P54 P53 [A06]# [3V3] [C10] P10 [3V3] [B10] P41 P40 [A05]# [5V0] [C11] P11 [5V0] [B11] P36 P35 [A04]# [C12] P12 [B12] P34 P33 [A03] [5V0]# [C13] P15 [B13] P32 P26 [A02] [3V3]# [C14] P16 [B14] P25 P23 [A01] [2V5]# [C15] P17 [B15] P22 P18 [A00] [GND]## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.CONFIG PROHIBIT=P99;CONFIG PROHIBIT=P43;CONFIG PROHIBIT=P42;CONFIG PROHIBIT=P39;CONFIG PROHIBIT=P49;CONFIG PROHIBIT=P48;CONFIG PROHIBIT=P47;CONFIG PART=XC3S500E-VQ100-4;NET CLK LOC="P89" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLKNET RX LOC="P90" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RXNET TX LOC="P88" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TXNET Seg7_AN(3) LOC="P18" | IOSTANDARD=LVTTL; # A0NET Seg7_DP LOC="P23" | IOSTANDARD=LVTTL; # A1NET Seg7_AN(2) LOC="P26" | IOSTANDARD=LVTTL; # A2NET Seg7_E LOC="P33" | IOSTANDARD=LVTTL; # A3NET Seg7_F LOC="P35" | IOSTANDARD=LVTTL; # A4NET Seg7_C LOC="P40" | IOSTANDARD=LVTTL; # A5NET Seg7_D LOC="P53" | IOSTANDARD=LVTTL; # A6NET Seg7_A LOC="P57" | IOSTANDARD=LVTTL; # A7NET Seg7_AN(1) LOC="P60" | IOSTANDARD=LVTTL; # A8NET Seg7_G LOC="P62" | IOSTANDARD=LVTTL; # A9NET Seg7_B LOC="P65" | IOSTANDARD=LVTTL; # A10NET Seg7_AN(0) LOC="P67" | IOSTANDARD=LVTTL; # A11NET SPI_CS LOC="P70" | IOSTANDARD=LVTTL; # A12NET SPI_MISO LOC="P79" | IOSTANDARD=LVTTL; # A13NET SPI_MOSI LOC="P84" | IOSTANDARD=LVTTL; # A14NET SPI_SCLK LOC="P86" | IOSTANDARD=LVTTL; # A15NET VGA_VSYNC LOC="P85" | IOSTANDARD=LVTTL; # B0NET VGA_HSYNC LOC="P83" | IOSTANDARD=LVTTL; # B1NET VGA_BLUE(0) LOC="P78" | IOSTANDARD=LVTTL; # B2NET VGA_BLUE(1) LOC="P71" | IOSTANDARD=LVTTL; # B3NET VGA_GREEN(0) LOC="P68" | IOSTANDARD=LVTTL; # B4NET VGA_GREEN(1) LOC="P66" | IOSTANDARD=LVTTL; # B5NET VGA_GREEN(2) LOC="P63" | IOSTANDARD=LVTTL; # B6NET VGA_RED(0) LOC="P61" | IOSTANDARD=LVTTL; # B7NET VGA_RED(1) LOC="P58" | IOSTANDARD=LVTTL; # B8NET VGA_RED(2) LOC="P54" | IOSTANDARD=LVTTL; # B9NET AUDIO LOC="P41" | IOSTANDARD=LVTTL; # B10NET JOY_RIGHT LOC="P36" | IOSTANDARD=LVTTL; # B11NET JOY_LEFT LOC="P34" | IOSTANDARD=LVTTL; # B12NET JOY_DOWN LOC="P32" | IOSTANDARD=LVTTL; # B13NET JOY_UP LOC="P25" | IOSTANDARD=LVTTL; # B14NET JOY_SELECT LOC="P22" | IOSTANDARD=LVTTL; # B15NET SWITCH(0) LOC="P91" | IOSTANDARD=LVTTL; # C0NET SWITCH(1) LOC="P92" | IOSTANDARD=LVTTL; # C1NET SWITCH(2) LOC="P94" | IOSTANDARD=LVTTL; # C2NET SWITCH(3) LOC="P95" | IOSTANDARD=LVTTL; # C3NET SWITCH(4) LOC="P98" | IOSTANDARD=LVTTL; # C4NET SWITCH(5) LOC="P2" | IOSTANDARD=LVTTL; # C5NET SWITCH(6) LOC="P3" | IOSTANDARD=LVTTL; # C6NET SWITCH(7) LOC="P4" | IOSTANDARD=LVTTL; # C7NET LED(0) LOC="P5" | IOSTANDARD=LVTTL; # C8NET LED(1) LOC="P9" | IOSTANDARD=LVTTL; # C9NET LED(2) LOC="P10" | IOSTANDARD=LVTTL; # C10NET LED(3) LOC="P11" | IOSTANDARD=LVTTL; # C11NET LED(4) LOC="P12" | IOSTANDARD=LVTTL; # C12NET LED(5) LOC="P15" | IOSTANDARD=LVTTL; # C13NET LED(6) LOC="P16" | IOSTANDARD=LVTTL; # C14NET LED(7) LOC="P17" | IOSTANDARD=LVTTL; # C15NET JTAG_TMS LOC="P75" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMSNET JTAG_TCK LOC="P77" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCKNET JTAG_TDI LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDINET JTAG_TDO LOC="P76" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDONET FLASH_CS LOC="P24" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CSNET FLASH_CK LOC="P50" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CKNET FLASH_SI LOC="P27" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SINET FLASH_SO LOC="P44" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SOWhich one of these nets is the MISO, MOSI, CS, and CLK for the ADC?
  3. terryphi

    Error When Driving Counter and DCM Simultaneously

    Sorry, I'm using the papillio one board, so it would be the Spartan 3 guide wouldn't it? Is this the relevant guide? http://www.xilinx.com/support/documentation/user_guides/ug331.pdf
  4. terryphi

    Error When Driving Counter and DCM Simultaneously

    Great, thank you! Given that, my other question I have is: how would I find this out without using the forums? Is there some sort of "clocked resources design guide" or something where I can read more about this?
  5. Hi There, I know 'can you please debug code' posts are generally frowned upon, but I'm having a bit of trouble with what, I think, should be a trivial problem. What I'm trying to do is connect the 32 Mhz clock pin to a counter as well as a DCM, but when I do this, I get the error "Port <CLK> has illegal connections. This port is connected to an input buffer and other components." When I hook the counter or DCM up separate, there is no issue. Can I only have the clock signal going to one location? Is there some sort of signal divider? My main VHDL file is as follows: ibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity main is Port ( LED : out STD_LOGIC_VECTOR (7 downto 0); SWITCH : in STD_LOGIC_VECTOR (7 downto 0); CLK : in STD_LOGIC); end main;architecture Behavioral of main issignal counter : STD_LOGIC_VECTOR(29 downto 0);COMPONENT cnt PORT( clock : IN std_logic; total : OUT std_logic_vector(29 downto 0) );END COMPONENT; COMPONENT dcm2 PORT( CLKIN_IN : IN std_logic; CLKFX_OUT : OUT std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic ); END COMPONENT;begin Inst_dcm2: dcm2 PORT MAP( CLKIN_IN => CLK, CLKFX_OUT => open, CLKIN_IBUFG_OUT => open, CLK0_OUT => open ); Inst_cnt: cnt PORT MAP( clock => CLK, total => counter );LED <= COUNTER(29 downto 22);end Behavioral;The counter code is: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity cnt is Port ( clock : in STD_LOGIC; total : out STD_LOGIC_VECTOR (29 downto 0));end cnt;architecture Behavioral of cnt issignal counter : STD_LOGIC_VECTOR(29 downto 0);beginclkProc : process(clock)begin if rising_edge(clock) then counter <= counter+5; end if; total <= counter;end process;end Behavioral;and the DCM setup is:
  6. terryphi

    Papilio One as High Speed DAQ

    200 Mhz would be perfectly fine for what I'm trying to do. Can you recommend any tutorial about how to accept commands from a UART? I've followed this tutorial: but it doesn't really explain how to send different types of data down the UART. Best Wishes. -TP
  7. terryphi

    Papilio One as High Speed DAQ

    Hello, I just bought a papilio one and logic start shield, and I'd like to use these as a high-speed data acquisition device. I'd like it to count pulses sent to it via an external pulse generator, then when it receives some sort of command from a computer, transmit to the computer how many pulses it had received since the last transmission request. I was hoping an experienced user could tell me how they would approach this problem. Best wishs, -TP
  8. terryphi

    Papilio One 500k - Speed Grade 4C

    Great! Thank you for your concise and informative answer!
  9. Hello, I have a Papilio One 500k, and I see on the chip, it is marked with a 4C speed grade. Now, does this correspond with the speed setting in the xilinx ise? What happens if I choose -5 instead of -4? Also, what does the 'C' refer to? I don't see any 'C' in the new project wizard's settings.