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Posts posted by ibullock

  1. Hi Filip,


    That quadrature decoder looks nice from my initial look. I am just starting to learn VHDL (used Verilog before). Basic PWM is fairly simple - some of the modules out there might be something fancier than what is needed.


    At 96MHz, we would want 4800 clock cycles to be one "cycle" of our PWM signal, in order to get 20kHz. That factor seems a little bit awkward but doable. If we used say a 10 bit counter for our main pwm (1024) states, we could have a prescaling counter which effectively divides the main clock by 5 (i.e. the main pwm counter is enabled to advance only every 5 cycles), which would give us 5120 clock cycles, or 18.75 kHz, which seems pretty good. (see e.g. http://www.fpga4fun.com/PWM_DAC_1.html for the very simple counter type design). I doubt I can hear 18.8 kHz sound at least :).


    I think you could also just do exactly 4800, but your input would have a more strange range (i.e. 0-4800 ish). I'm not sure if it's too important to hit 20kHz exactly though. The previous version is if you still want the full range to be a power of 2 (e.g. the full range of a 10 bit input bus).


    I haven't completely thought it through, there may be a much better way to do it. But hope that helps to give you ideas! (see also http://www.fpga4fun.com/PWM_DAC_1.html)

  2. Thanks again, got it to run with a custom SoC with some counters attached to the Wishbone_to_Registers module just as a test. It's great how easy it is to hook various things to that module. I think it took me most of the time to figure out how the stupid bus taps work and also the REGISTER(IO_SLOT(wishbone_slot),0); syntax.


    Was confused about how to get a .bmm file to use with Papilio Loader (actually wasn't sure how to export the .hex either but that should be easier to find info on)... does the Loader somehow magically figure everything out from just specifying the single bit file? If I use the loader with just the bitfile specified and then disconnect/reconnect USB, reset the fpga, etc. it seems to have my custom sketch (and SoC) loaded correctly still. Obviously not complaining if that's all I have to do each time, but just curious...

  3. Hi Jack,


    I think that's what happened - I didn't think I modified any of those projects at all, but I believe due to Xilinx autosaving the project, and the template projects being unable to find some of those files, it must have somehow modified how those files were set up in the template just from opening the project. Anyway, after reinstall it can get all the way through Generate Programing File with only warnings (which I should go back and check probably), so I think things are on the right track now. Thank you!


    Question - if you do edit circuit before resaving the .ino in a new location, will that break things? Maybe that's what happened? This time, I saved the .ino somewhere else first, and then hit edit circuit (it prompted me to pick a directory again.) I picked the same directory which gave a very strange error message about an infinite loop or somesuch, but seems to have worked okay? Not too important now, just figured if you know what I did wrong it could help to make future software more user-error-proof if desired.


    - Ian

  4. What I meant is that there seem to be duplicate copies of certain files in the DesignLab 1.0.5 directory structure. For example, sram_ctrl8.vhd is present in C:\DesignLab-1.0.5\examples\00.Papilio_Schematic_Library\Libraries\ZPUino_1\PSL_Papilio_DUO_LX9 and also C:\DesignLab-1.0.5\libraries\ZPUino_2 . They appear to be similar but not identical. The imports in each one are a tiny bit different, for example, although both of them include work.zpu_config.all ... work.zpupkg. One of them adds work.wishbonepkg.all, and one of them imports unisim after the zpu .. stuff, the other one imports it before. I'm not sure if this actually has anything to do with the current issue, but I thought I would mention it just in case.


    Just FYI: I do get this when I first run Xilinx - but I'm not sure it's actually important:

    Launching Design Summary/Report Viewer...WARNING:ProjectMgmt:430 - DesignStrategies - Strategy file C:/Xilinx/14.3/ISE_DS/ISE/data/default.xds doesn't exist or is empty, skipping.

    (Somewhat odd because my Xilinx directory is D:\Xilinx\14.7 .)


    I used the uninstaller for DesignLab 1.0.4 and installed 1.0.5. I have removed any remnants of the original 1.0.4 structure so hopefully any old versions are safely removed.


    I tried to attach the .xise directly but it wouldn't let me. So, I renamed it to a .txt. Please rename back to .xise if you want to take a look. Thank you!




    I will do an extra computer restart too to see if it magically fixes anything. Currently still getting the same Cannot find <zpu_config> in library <designlab>... etc errors. Sorry for the trouble when this is probably something pretty obvious - but I guess maybe I won't be the only one to run into this issue either? Thanks!

  5. Yes, it does have that - I am a bit confused by the error. I did notice there appear to be duplicate versions of certain files in different locations (though I checked the sram_ctrl8.vhd file and I think only 1 version is imported in my ISE project, from libraries\ZPUino_2). My sram_ctrl8.vhd file starts with:

    library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;use ieee.std_logic_unsigned.all;library unisim;use unisim.vcomponents.all;library work;use work.zpu_config.all;use work.zpuino_config.all;use work.zpupkg.all;use work.zpuinopkg.all;entity sram_ctrl8 is

    It is also throwing errors such as "ERROR:HDLCompiler:69 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" Line 54: <std_logic_vector> is not declared." But when I searched for those, I think those usually just result from another error, such as a syntax error, in another part of the file.


    I have just been running "implement top module" - do I need to do any other steps prior to that?


    Let me know if there is any other info I can give you to try to diagnose. Thank you!

  6. Hi Jack - Thank you (on both counts) - I tried through edit circuit, and it did import.... quite a lot more things. However, I am still getting some errors during synthesis (Saving a new project from Papilio_DUO_Quickstart, or New_ZPUino_SOC seems to give same errors.


    Parsing VHDL file "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" into library DesignLab
    ERROR:HDLCompiler:104 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" Line 10: Cannot find <zpu_config> in library <designlab>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
    ERROR:HDLCompiler:104 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" Line 11: Cannot find <zpuino_config> in library <designlab>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
    ERROR:HDLCompiler:104 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" Line 12: Cannot find <zpupkg> in library <designlab>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
    ERROR:HDLCompiler:104 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" Line 13: Cannot find <zpuinopkg> in library <designlab>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.


    Seems a bit confusing to me because when you look at the file, it appears to be trying to load from the "work" library, which is where those files are loaded. So, I'm not sure why the error message mentions "designlab." Anyway hopefully just something trivial I am missing... Thanks!

  7. Okay, managed to fix most of those by adding various files to the project, but still stuck on an error:


    WARNING:HDLCompiler:89 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\ZPUino_Papilio_DUO_V2.vhd" Line 176: <zpuino_papilio_duo_v2_blackbox> remains a black-box since it has no binding entity.


    Since I included things haphazardly from different locations, I'm not super confident that the schematic symbols all correspond to the right version of the vhd file - maybe that could be causing problems?


    I do have ZPUino_Papilio_DUO_V2_blackbox.ngc included which I thought would resolve that but didn't.


    I did have to add a bunch of files from DesignLab-1.0.5\examples\00.Papilio_Schematic_Library\Libraries\ZPUino_1\PSL_Papilio_DUO_LX9\ - that seems like maybe a bad thing since the directory implies the files should be for ZPUino_1 rather than ZPUino_2.




    P.S. for any of you on Windows 8 64-bit, running 32-bit Xilinx project manager seems to be the way to go to avoid it crashing every time a file dialog box is needed.

  8. Hi Jack - Thanks for those answers so far. I have upgraded to DesignLab 1.0.5 now (Win 8.1 x64) but am still getting missing file errors when I open PSL_Papilio_DUO_LX9.xise in a "save-as" version of the ZPUino_Vanilla circuit


    WARNING:ProjectMgmt - File C:/imb23repos/fpga/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpuinopkg.vhd is missing.
    WARNING:ProjectMgmt - File C:/imb23repos/fpga/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpuino_config.vhd is missing.
    WARNING:ProjectMgmt - File C:/imb23repos/fpga/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpupkg.vhd is missing.
    WARNING:ProjectMgmt - File C:/imb23repos/fpga/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpu_config.vhd is missing.
    WARNING:ProjectMgmt - File C:/imb23repos/DesignLab/build/windows/work/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/papilio_duo.ucf is missing.
    WARNING:ProjectMgmt - File C:/imb23repos/DesignLab/build/windows/work/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/Utility.sch is missing.


    When I open the schematic I also get


    ERROR: Could not find symbol "Wing_GPIO"

    ERROR: Could not find symbol "Papilio_DUO_Wing_Pinout"

    ERROR: Could not find symbol "ZPUino_Papilio_DUO_V2"


    I am assuming I just need to add some extra library path somehow for the latter issues. Is there a reference already somewhere on how to set this up?



  9. So, this seems like an okay place to post some new user questions? Here goes:


    My overall goal at the moment is to implement some simple modules on the FPGA for motor control, including a quadrature encoder reader and a small module to do PWM and direction control output to a VNH5019A motor driver (basically just fancy H bridge with some protection stuff). Basically trying to do the fast/low level stuff with dedicated modules on the FPGA, and then use either ZPUino or the MEGA32U4 for higher level control. I do have some experience with FPGAs / Xilinx (mainly with Verilog, haven't used the schematic editor in a long time.) So mostly the obstacle has been figuring out how things are setup for the Papilio specifically. Some questions: 


    (I am using windows 8.1 x64, Papilio DUO, DesignLab 1.0.4, Xilinx WebPack 14.7)


    - Some of the stuff I want to implement (e.g. quadrature encoder stuff) should have direct access to fpga pins. I'm slightly confused by how the Papilio_DUO_Pinout block is setup in the schematics. For example, if I want to wire for example pins Arduino 53 through Arduino 39 (odd) to my own module, should i just sever the current connection to these pins from the "Papilio DUO Pinout" block, connect them to my own block instead, and then connect my own block e.g. to one of the wishbone bus slots somehow? It seems this should work, but I don't really know if it is the "correct" way to do it or more of a hack.

    - When I try to open a Xilinx project made from Papilio_DUO_Quickstart, it seems to be missing ZPUino_1 files. Is there a way to get these files? I see ZPUino_2 FPGA stuff in my libraries folder, but not ZPUino_1.

    - Is there a standard way set up to transfer data between the hardware AVR and ZPUino? I see some AVR_Wishbone bridge type thing referred to here and there, but when looking at the 1 or 2 example projects that seem to relate to this, it is hard for me to even figure out what processor the code is supposed to be uploaded to. Is this a work in progress or something that works already / has been used?

    - I was slightly surprised to see the separate oscillator for the AVR and FPGA as it seems it could make data transfer between the two more difficult, but I don't know too much about the tradeoffs/requirements in implementing these things. Are there any nice ways to sync up a clock in the FPGA with the AVR? Just seems it might help in reducing the complexity of data transfer, e.g. you could possibly just read/write bits directly across sometimes without having to use synchronizers/FIFO/etc. Anyway, mostly just curious if there is an easy solution, such as outputting the clock from the AVR on some pin, which is then used to setup a synchronized clock in the FPGA.

    - Any nice example code in general I should be looking at to better understand how to accomplish some of these things?


    Sorry if that is a bunch of questions at once but hopefully mostly not too difficult to answer. Thank you!