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About Cactus

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  1. Cactus

    What is a good source of reset signal?

    Thank you! I have now done just that, and it works. Wrapping the whole design into a toplevel VHDL module is a bit of a bummer (since I now have to manually "forward" all real IO from the real Clash code to the IO of this wrapper), but I think there should be a way around that by somehow getting Clash to automagically instantiate a VHDL part and thereby avoid this inversion of structure. Wouldn't that still have that problem of too much fanout, like in the original Xilinx warning?
  2. I'd like to use CLaSH ( with a Papilio Pro. By and large, it works; however, CLaSH requires an asynchronous, active-high reset spike to initialize registers. This is because CLaSH generates assignments on RESET only, instead of initializers; here's an example VHDL generated from CLaSH: -- Automatically generated VHDL-93 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; use std.textio.all; use work.all; use work.blinkertop_types.all; entity blinkerTop is port(-- clock CLK_32MHZ : in std_logic; -- asynchronous reset: active high RESET : in std_logic; LED : out std_logic); end; architecture structural of blinkerTop is signal \#tup_app_arg\ : unsigned(31 downto 0); signal \s'\ : boolean; signal \#s'_case_alt\ : boolean; signal s : boolean; signal \#finished_case_alt\ : boolean; signal \#k'_case_alt\ : unsigned(31 downto 0); signal ds : blinkertop_types.tup2; signal \#finished_app_arg\ : signed(63 downto 0); signal x : unsigned(63 downto 0); signal x_0 : blinkertop_types.tup2; signal \x#\ : unsigned(63 downto 0); signal k : unsigned(31 downto 0); signal \#w\ : unsigned(63 downto 0); begin LED <= '1' when \s'\ else '0'; \#tup_app_arg\ <= resize(to_unsigned(0,64),32) when \#finished_case_alt\ else \#k'_case_alt\; \s'\ <= \#s'_case_alt\ when \#finished_case_alt\ else s; \#s'_case_alt\ <= false when s else true; s <= ds.tup2_sel0; \#finished_case_alt\ <= tagToEnum(\#finished_app_arg\); \#w\ <= (\x#\ + to_unsigned(1,64)); \#k'_case_alt\ <= resize((resize(\#w\(31 downto 0),64)),32); -- register begin blinkertop_register : process(CLK_32MHZ,RESET) begin if RESET = '1' then ds <= ( tup2_sel0 => false, tup2_sel1 => resize(to_unsigned(0,64),32) ) -- pragma translate_off after 1 ps -- pragma translate_on ; elsif rising_edge(CLK_32MHZ) then ds <= x_0 -- pragma translate_off after 1 ps -- pragma translate_on ; end if; end process; -- register end \#finished_app_arg\ <= to_signed(1,64) when x = to_unsigned(32000000,64) else to_signed(0,64); x <= resize(\#k'_case_alt\,64); x_0 <= ( tup2_sel0 => \s'\ , tup2_sel1 => \#tup_app_arg\ ); \x#\ <= resize(k,64); k <= ds.tup2_sel1; end; (Note how `ds` is not initialized but set in the `blinkertop_register` process when RESET is high) Of course, for a simple circuilt like above, where the initialization is for 0 anyway, just setting RESET to always low works; however, any slightly more complicated circuit will need register initialization to non-0 values as well. In these cases, I really need the spike. Is there a pin on the Papilio Pro that I could use in my UCF file to get this reset spike? I was able to get it working, in more complicated circuits requiring non-0 initialization, by using a (negated) LogicStart joystick direction, but this approach has two problems: I am getting a warning from the Xilinx tools that the joystick input shouldn't be used for reset or anything clock-like: WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component <RESET> is placed at site <P57>. The corresponding BUFG component <RESET_IBUF_BUFG> is placed at site <BUFGMUX_X3Y13>. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <RESET.PAD> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. I would like my circuit to start in an initialized state instead of requiring me to press a button
  3. I just got the PS/2 wings in the mail, thank you! I've meanwhile manned up and made a PS/2-to-breadboard adapter by soldering a PS/2 connector to a stripboard; that went well apart from mixing up GND and Vcc on the first try, frying the keyboard... Check the result:
  4. Thanks, by moving the Arcade MegaWing (instead of flipping), and using P85/P83 of the Papilio One as the PS/2 DATA/CLK lines, I got it working. However, my schedule has also changed, and so I might have enough time to wait for the PS/2 wing, so I'll be taking you up on your offer. I'll send my shipping details in a private email. Thanks a lot!
  5. Cactus

    Output voltage on pins

    Thanks; I've tried and managed to drive the 5V device (a 1602 LCD) with the 3.3V signals (and 5V power of course).
  6. Thanks a lot Jack, I might take you up on that offer -- but I'm in Singapore and I'd like to build this in time to show it off at a meetup in two weeks' time, so waiting for extra parts is not an option. So will a flipped Arcade MegaWing work?
  7. Cactus

    Output voltage on pins

    Thanks, that's very helpful. And what if I need to do output to a 5V device? I guess I could use one transistor per line, but is there an easier way?
  8. For my next project, I need to use a PS/2 keyboard as an input device, and a 1602 LCD module for output. This means I will need a PS/2 port and some free pins (six to be exact) at the same time. What options do I have if I don't have a standalone PS/2 wing? My current plan is to take an Arcade MegaWing, and put it on a Papilio One flipped, i.e. by leaving the connector marked U$1WING2 free, and then use some male-to-male jumper cables on that connector to connect to the LCD on a breadboard. By re-mapping the pins in the UCF file, I should be able to get one of the PS/2 connectors working that way, right? Is there a better way to achieve this?
  9. Cactus

    Output voltage on pins

    What is the output voltage level for 'high' signals on the Papilio Pro? I'd like to communicate with 3.3V components from it, is that possible by just connecting directly to the pins? I see there are separate 3.3V and 5V power pins. If I have a component that requires 3.3V signals and another that requires 5V, is there a way to communicate with both with a single Papilio Pro?
  10. So, on a Papilio One 500k, I would use bscan_spi_xc3s500e.bit as the -b file? And the Java GUI just auto-detects it and picks the right one?
  11. Hi, I can use papilio-prog -f foo.bit to upload my bitstream to RAM, or I can use the Java GUI to flash it. Is there a way to use papilio-prog to flash to SPI from the command line? The obvious flag would seem to be -b, but that just results in: Please specify main bit file (-f <bitfile>)
  12. Cactus

    PS/2 ports on Arcade MegaWing

    Thank you everyone for your help -- the solution was indeed to get a proper PS/2 keyboard. Now all the test configurations work as expected.
  13. Cactus

    PS/2 ports on Arcade MegaWing

    I'll try getting a true PS/2 keyboard and will report back.
  14. Cactus

    PS/2 ports on Arcade MegaWing

    Alex: Thanks! Can you maybe send me a bitfile for testing? I am now at the point where I'd like to make sure the hardware (incl. the usb -> ps2 dongle!) is working before looking at anything else.
  15. Cactus

    PS/2 ports on Arcade MegaWing

    I have now also tried the code from, by connecting joy_up directly to one of the LEDs. If I understand correctly, that should result in the LED lighting up as long as I am pushing the left cursor key on the keyboard, right? Still doesn't work.