hamster

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hamster last won the day on April 28 2020

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  1. That is like designing a rally car and asking if for best perfomance you should use racing slicks.... Let your engineers use whichever tool works for them - but it won't be C++!
  2. WIth 100 boards you won't be at the point where the engineering costs for your own PCBs start making sense over an off-the-shelf board, unless you have other constraints that make it very important to you. If a off-the-shelf costs $1,500, it might have a build cost of about $500 per board, so you only get $100,000 for board development and tested before it isn't worth it financially, and that doesn't include any allowance for the risks and the development time. Given that you could pay a little more and get some fully-featured dev boards on your desk tomorrow that people can work with straight away, verses a complex PCB development, including the associated risk and expenses it seems a no-brainier. You always have the option of designing a custom board once things are up and running and your requirements have been are completely understood. I would think that it is a very limited skills pool - FPGA/ASIC, low latency designs, high speed comms, most likely gigabit networking , tcp/ip protocols, the understanding of the on-the-wire trading protocols, and then implementing HFT algorithms. The pool of people would be very small - about the same size as a niche medical specialist (e.g. in the same order as Orthopedic surgeons who specialize in jaw reconstructions). Defiantly not main-stream skills.
  3. Hi oritemis.frc, I can give you an none-answer. We don't really have enough specs to give you a sensible answer. Say you wanted the top level of performance the entry price is pretty steep. If you wanted to accept multiple 10 Gbps fibers the hardware alone will cost something like $10k per instance. (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1328&Prod=NETFPGA-10G-SUME). If you only need multiple Gigabit interfaces the hardware is about $1.5k per board.. Tools to develop the application will cost $3k+ per year per seat. Any IP you license will also cost, like a wounded bull - for example a SATA IP block costs $20k per design. H/W cost is only a small bit. Engineering time will cost about $100k p.a. for an average VHDL engineer (see http://www.payscale.com/research/US/Skill=VHDL/Salary).Maybe $1k a day for a contractor. It would need a small team outside of the developers of main trading algorithm. - Software - embedded Linux will most likely be in there somewhere - A networking protocol engineer. - Programmable logic - maybe three engineers, or one really enthusiastic one. - Testing / Verification (e.g. making dummy feeds, testing benchmarking and so on. - Ongoing support. If you wanted to build custom boards you will need a high speed design engineer or two, and maybe $100k (if not more) for prototypes Development time frame really depends on system complexity - maybe 4 weeks, maybe 6 months. So as a rough budget. - hardware and setup for 5 engineers - maybe $100k. - Development resource (5 engineers for 6 months) - $8k per week per month per engineer = $240k - Office space, expenses, travel... - Contingency Call it $400k, on the back of an envelope, without actually knowning what you want to do.
  4. Make sure you have software flow control turned off on the pprt , or you will lose all you XON/XOFF characters. (\x11 and \x13 IIRC) Mike
  5. An old trick is you can clock a BRAM with "not clk" and the result of a lookup is ready before the next rising clock edge... However your designs Fmax might halve so it isn't suited for high performance designs.
  6. To me speed grades are really confusing - in practice they are just the set of parameters that the device is guaranteed to meet, allowing the tools to ensure that you have a reliable design. For example the time required from a clock ticking to the output being available on the output of a Configurable Logic Block (CLB) Grade -3 = 0.45 nsGrade -3N = 0.53 nsGrade -2 = 0.53 nsGrade -1L = 0.74 ns (from http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf) A bitstream for a -2 device will work on a -3 device, but even the simplest design implemented at for -3 device can in theory fail on a -2. The placement of resource and routing is timing aware, and the tools ensure that the design's timing meets the devices requirements. The tools stop at good enough - all it needs is 0.001 ns slack and timing is met. If you want that bit file to work on a -2 grade you need an at least an extra 0.08 ns for the slower output time, and another 0.05 ns for the slower set-up time, and another 0.05 for each level of logic in the path - it soon adds up!
  7. The max speed up the serial port is about 3Mbits/s, and at that speed most PCs have problems with input latency issues and/or the buffers getting swamped, causing data to be dropped. You sound as though you have a special design in mind? I've managed to get a Digilent Nexys2 board transferring at about 10MBytes/s (see http://hamsterworks.co.nz/mediawiki/index.php/Digilent_EPP_Performance), but you will need to use all the block RAM on the FPGA as a FIFO - if the PC has to pause for a 5ms for a disk I/O that requires 50KB of buffering on the FPGA!
  8. So I've just finished my latest project - an FPGA based FM transmitter that beeps out SOS in Morse code. All you need is a wire and 60 lines of VHDL! http://hamsterworks....ndex.php/FM_SOS I was musing over it all day and decided to give it a try. There I was feeling extra clever at how well it works, and upload the a video of it in operation to Youtube. As soon as it finished it recommends that I might want to watch another video - it is somebody transmitting music on FM using only an FPGA. I don't feel so clever now! Original forum thread.
  9. Click here for the original forum topic I've just finished my 8 digit frequency counter - I'm just waiting for a GPS module to arrive so I can use it as the reference timesource. Here's a block diagram of the project: And here is a photo of it in action, when using a one pulse per second generated from the local Xtal as the reference. Full source is up on my wiki at http://hamsterworks....equency_counter
  10. Ever thought of maintaining a map of Papilio's World Domination, and putting a red dot on when a n order ships? I know that at least a few exist here in New Zealand!
  11. Other tricks you can do are: Spin the Wings A+B connector block around 180 degrees, and you should have access to everything but the LEDs and slide switches, plus 16 pins of I/O. Plug the WIng B pins into the WingC socket and have VGA, Joystick, audio and 32 pins of I/O. Of course you have to update your UCF files. Here is my updated UCF file for using the Switches and LEDs - Please note I number my LEDs wth LED0 on the right and LED7 on the left - the opposite way to the silk screening! # LogicStart Megawing with Wing C only plugged into the Wing B socket NET switches(7) LOC = "P85" ; NET switches(6) LOC = "P83" ; NET switches(5) LOC = "P78" ; NET switches(4) LOC = "P71" ; NET switches(3) LOC = "P68" ; NET switches(2) LOC = "P66" ; NET switches(1) LOC = "P63" ; NET switches(0) LOC = "P61" ; NET LEDs(7) LOC = "P58" ; NET LEDs(6) LOC = "P54" ; NET LEDs(5) LOC = "P41" ; NET LEDs(4) LOC = "P36" ; NET LEDs(3) LOC = "P34" ; NET LEDs(2) LOC = "P32" ; NET LEDs(1) LOC = "P25" ; NET LEDs(0) LOC = "P22" ;
  12. I've finally got my 'Synth' project to the point that it can act as an OK sounding music box: http://www.hamsterwo.../Synth_Envelope http://youtu.be/XRITkbgBR4c It plays Brahms Lullaby in monophonic glory! One pair of switches changes between a Sine wave and a richer waveform I made in a spreadsheet. Other pairs control the envelope (Attack, decay and release rates). I'm thinking of using the ADC on the LogicStart to give me analogue control inputs... It only 'does stuff' one clock cycle in 666 of the 32MHz clock, so there is plenty of scope to move to direct digital synthesis or massive polyphony. Buried on the related pages are the C utilities to convert arrays to either 9 or 18 bit BRAM VHDL instances... Full discussion thread
  13. I like the LogicStart,,, but then I'm biased!

  14. In the past I've been playing around with RS232 and found it quick and simple to use from both the interface from both the FPGA design and the client software, so I sketched out a design and over a couple of nights CheepScope was born! It features: * 16 channels * 1024 samples * Requires only one I/O pin - or no pins if your Dev board has a USB to RS232 interface * Light on resources - one Block RAM and about 100 slices. I've made a very simple character mode user interface for use under Linux. It is functional but not flash. It is not as good as the Vendor's VLA as it needs to be added to your design it is built, but it works a treat. It's all up on my Wiki at http://hamsterworks.....php/CheapScope If (like me) you don't run Linux natively you can always use Virtual Box's USB device pass-through, allowing your VM to see the USB-to-Serial device.
  15. I've just got DVI-D running on a Spartan 6, starting from scratch (well, the DDWG specs at http://www.ddwg.org/downloads.asp ) You can find the details of my project (incl all the vhdl source) here: http://hamsterworks....x.php/Dvid_test Feel free to use it in your own projects. Wonder if it will work on the Papilio Pro? Might have to butcher a cheap HDMI cable... Mike This post was covered on Hackaday too. http://hackaday.com/...m-vga-to-dvi-d/