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About This File

We live in exciting times where we can create masterpieces with the Arduino and marvels with the Raspberry Pi. Where we can use technology as a canvas to create things that amaze and amuse our friends and family. Wouldn't it be great if we could take the same technology that has been the staple of rocket scientists and put it in our creative arsenal? Without the need tobecome a rocket scientist or the headache of learning a new programming language like VHDL/Verilog.

Why can't we just draw up the circuits that we want to use? With the right software and circuit libraries we can! Let's put a full circuit lab on a chip, pair it with an easy to use Arduino-Compatible chip, and sprinkle in a generous helping of debugging tools.

Our dream is to take the hardcore out of FPGA (Field Programmable Gate Array) and make it an amazing tool that anyone can use for creative technology projects.

Just like the Arduino team simplified C++ programming, we simplify FPGA design by providing easy to use drag and drop circuit libraries. We believe that drawing circuits will result in an amazing outpouring of creative FPGA projects!

We start with the Arduino IDE (Integrated Development Environment) and supercharge it by adding circuits into the mix. We bring all of the pieces needed to draw and debug your very own circuits in one place. It's an easy and seamless user experience that we call Papilio DesignLab for use with both Windows and Linux.

Want to get into more complex circuits? DesignLab includes the ZPUino Soft Processor with a Wishbone bus, providing greater speed and flexibility than the Arduino-Compatible chip. A Soft Processor runs inside the FPGA and uses the Wishbone bus to make it easy to connect peripheral circuits, such as UARTs, PWMs or SPI masters. Making your own Soft Processor with just the right mix of peripheral circuits is known as a SOC (System On Chip) design. With DesignLab you can draw your SOC designs in minutes!

Create SOCs with ten serial ports, or a PWM on every pin, or something exotic like classic Atari and Commodore audio chips connected at the same time. The sky is the limit, you can create things that don't exist anywhere else!

DesignLab Circuit Library

Drawing circuits can only accomplish so much without a library of circuits (known as cores) to do the heavy lifting. Our goal is to provide the framework for anyone to write a core that can be wired into a circuit.

We want to seek out the best open source circuits on the interwebs and convert them to a dead simple schematic library. The internet is absolutely full of open source circuits; just take a look at sites like OpenCores.com. You will find everything from classic audio chips to stepper motor controllers. All of these amazing circuits are within our reach when converted to schematic form and included with DesignLab IDE!

What's New in Version 1.0.8   See changelog


DesignLab 1.0.8 - 2017.01.04
[DesignLab Libraries]
    -Added a new Video Audio Player example.
    -Fixes for RetroCade Synth libraries.

  • DesignLab 1.0.7 - 2015.06.16
  • [ide]
  • -Fix problem with saving a new project and then having to save again when opening library.
  • -When opening Logic Analyzer project there is now an option to load a LA bit file to the FPGA.
  • -LA icon added to menu bar.
  • [DesignLab Libraries]
  • -Benchy Logic Analyzer library updated with 16 and 32 Channel circuit symbols.
  • -SmartMatrix RGB Panel Library added. (Color Correction not enabled.)
  • -RGB Panel circuit symbol and wing symbol added.
  • -1-Pixel Pacman working with SmartMatrix RGB Panel library.
  • -Animated GIFs working with SmartMatrix RGB Panel library.
  • -Add Wing buses to ucf files.
  • -Gameduino library fixed and fully working again.

User Feedback

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On linux ext file system, where capitalization matters, the Xilinx ISE project file circuit/PSL_Papilio_One_250K.xise has Upper case 'K', but the link in designLab the "New DesignLab Library" sketch template has " sketchdir://circuit/PSL_Papilio_One_250k.xise" with a lower-case 'K'. This results in an error when you invoke ISE by clicking on that link. Are these names coming from hardware/zpuino/zpu20/boards.txt? If so, other entries seem to have similar problems with .bit, .sch, and etc. files. Similar things happens with the .bit file. In the case of the .bit file, there's a default blank library already under the correct name, papilio_one_250k.bit. So when you think you're loading your circuit which is created under Papilio_One_250K.bit, the blank circuit is getting loaded. It took me some time to figure this out.

I found, in the forum which I hadn't searched until now, others reporting similar problems as well.

After spending so many hours jumping over these hurdles, I was finally able to use ZPUino with a wishbone peripheral of my own creation. Although I am complaining on usability and stiff learning curve, Papilio and DesignLab are still great stuff! Great Job, Jack!

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