I wanted to add cheap, generic interactivity to VHDL projects, to replace AVR8 sketches, which are great but expensive, and not extendable "in situ" (you need to compile the new sketch and flash your FPGA)
My goal is to provide a full Forth system, that allows the control and programming of FPGA projects through a UART console, without taking too much of the FPGA resources. Forth is good for that because it is very simple, produces very compact code (99% calls to subroutines) and allows the on-the-fly compling of new code on a live system.
To keep things small and fast, I designed a custom processor, with two stacks and only two general purpose registers, with a simple, RISC-like, machine code. The "machine" itself is very small (~7% of a Papilio 500), and uses only 3 ram blocks (1 for stacks, 2 for program/data memory) It seems to work fine, except for the custom UART, which is still a bit buggy (timing problems -- a shame at 9600 bauds...)
It's designed to be easily extensible, using memory mapped devices, so you can use it as an interface to your cores.
The Forth system itself is still very beta, but you can already define words and do some simple arithmetic and io. I implemented a basic "compiler/assembler" and a simulator (both in Java).
Next steps are 1) complete the Forth system and 2) debug the thing thoroughly so it can be used seriously. V0 is on GitHub, at https://github.com/b...9/Papilio-Forth
And more info on Forth on http://www.softsynth...rth/pf_tut.php.
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