Flavia: the Free Logic Array

  • Make small Digital Logic designs without the heavyweight vendor tools. Flavia tool chain lets you make bit files for the Papilio One 250K with completely FLOSS software! Only CPLD sized designs are possible, but this is a boon for learning Digital Logic on ARM based boards like the Raspberry Pi. http://ow.ly/AN3OV

Flavia, the Free Logic Array, is a programmable device intended primarily as a teaching tool for FPGAs and CPLDs. Unlike every commercial device I'm aware of, Flavia's tool suite is free-as-in-liberty open-source software (FLOSS). This means it can run on platforms other than x86 PCs, including Raspberry Pi (tested) and BeagleBoard/Bone (not fully tested yet).

Flavia is a "CPLD in an FPGA", which uses FPGA look-up tables (LUTs) to implement both logic and routing. Since Xilinx documents ways to find the locations of your LUTs and flip-flops in their otherwise undocumented bitstreams, it's possible to program those LUTs to make a reasonably nice CPLD that can be programmed using FLOSS tools.

Flavia's first implementation uses the Papilio One 250K as its underlying FPGA. The 250K Spartan-3E FPGA has enough logic resources to make a useful CPLD and the FT2232D provides an easy programming interface for Flavia's software.

If you're interested, take a look at my 'blog at element14, which has links to all the software and documentation.

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Flavia is now available for the Papilio One 500K!  The new "FlaviaP48" implementation is part of XXICC rev 0.0m, released 15 November 2014.  The software and documentation are in this 'blog at element14.


In addition, you can now set the Flavia clock to values from 1 Hz to 32 MHz instead of being stuck with the 2 Hz "proof of concept" clock.

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Flavia is now available for the Papilio DUO!  See my 'blog at element14: Raspberry Pi 2 meets Papilio DUO.  The 'blog talks about using a RasPi 2 as the Flavia host, but the rev 0.0p software works on other GNU/Linux platforms.  I haven't tried it on Windows yet.


The Papilio DUO version of Flavia allows you to configure pull-up, pull-down, and keeper circuits for I/Os.  I'm working on adding this to the Papilio One versions.

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