papry

SUMP ported to a new hardware platform

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Apologies as this is obviously somewhat off topic (different hardware).

Previously I have compiled the VHDL source of the SUMP code for the Papilio One and successfully used it with the 5V level translater wings. This solution is incredible value, as even 8 or 16 bit logic "hobbiest" logic analysers cost many hundreds of dollars.

Recently I bought a cheap FPGA board called the RV901T from China. I has 64 I/Os at 5V level (grouped into banks of 32). There are some direct FPGA connections too. However a stand alone Xilinx programmer is required and soldering skills to wire up the JTAG pins. The board has a Xilinx Spartan6 (like the Papilio Pro) but bigger (XC6SLX16). The original article was on Hackaday.

So I started to write Verilog code to check that each pin toggled and that the direct FPGA pins could support serial comms using my own UART code. Good job I checked because I did need to remove a pull down resistor pack.

Having got this far I decided to try to code my own logic analyser to be compatible with the OLD protocol and software. After a few bugs have been fixed from the LogicSniffer GUI I can get it to read the meta data.

Question - can the device string be anything or for it to work does the software expect certain strings (device types)?

Question - does anyone have a larger dump of all transactions over the serial comm port?

Reason is I think the OLS protocol is not completely documented. Although the GUI sees the meta data it doesn't appear to ask for a capture. Perhaps it doesn't recognise my device "RV901T"?

Any answers would be much appreciated. I intend to put the completed code on Github for others to use.

BTW I was aware of the Pipistrello Verilog code which was helpfully posted in a earlier posting in this forum section. I have taken a look, but found the code hard to read.

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