Place:1108 in a XC6SLX16-CSG324


Oskar STEPIEÑ

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Hi,

I´m making a emulatorfor an FPGA Spartan6 XC6SLX16-CSG324C (Its a Nexys 3 board). When I tried make something more complex than light an LED, I though the problem was mine. But, I tried make a simple program to know the issue.

This program, a simple botton-led, I use the C4 pin and U16 pin.

The problem is the C4, a button, does the next error.

Quote

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <btnl> is placed at site <C4>. The corresponding BUFG component
   <btnl_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y12>. There is only a
select
   set of IOBs that can use the fast path to the Clocker buffer, and they are
   not being used. You may want to analyze why this problem exists and correct
   it. If this sub optimal condition is acceptable for this design, you may use
   the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message
   to a WARNING and allow your design to continue. However, the use of this
   override is highly discouraged as it may lead to very poor timing results. It
   is recommended that this error condition be corrected in the design. A list
   of all the COMP.PINs used in this clock placement rule is listed below. These
   examples can be used directly in the .ucf file to override this clock rule.
   < NET "
btnl" CLOCK_DEDICATED_ROUTE = FALSE; >

Alright, some good being, told me to use the solution of:

1- Change the button to other that works (Works fine, but... there only works 3 buttons from 6, and one is the RESET button)

2- Use the "NET "btnl" CLOCK_DEDICATED_ROUTE = FALSE;", this, doesn´t work fine in the board.

 

I looking for any new solution that might work. I also have the original proyect that don´t have any of this issues, but it´s a bit strange.

 

The code is the next:

Quote

module blink(
     input btnl,
    output led0,

    );
    
reg ledst0;
    always @(posedge btnl)
    ledst0 <= !ledst0;
    
    assign led0 = ledst0;

endmodule

1

And the .ucf file:

Quote

NET "led0" LOC = U16;

NET "btnl" LOC = C4;

 

Any help would be apreciated.

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Here is the problem - you take the signal from the button connected to pin C4 and use that as a clock for the ledst0 flip-flop.  This is not how you use an FPGA.  Pin C4 is not a clock input pin, which cause the error 1108 you see, and logic signals like btnl should not be used as a clock.

FPGAs are intended to be used for synchronous logic designs where a large number of flip-flops are clocked with a common clock.  In order to make this possible the clock is distributed to all the flip-flops in this clock domain using special clock buffers and clock networks.  The source of the clock is typically coming from an input pin on the FPGA and only a select few pins can be used as clock input.  The input clock can be used as is or can be feed to a clock management tile that has resources like PLLs and DCMs that allow you to create a clock with different clock frequency. 

The Nexys3 board has a 100 MHz clock input signal connected to pin V10 that can be used as system clock.  This is what the Nexys3 manual states:

Quote

The Nexys3 board includes a single 100MHz CMOS oscillator connected to pin V10 (V10 is the GCLK0 input in bank 2). The input clock can drive any or all of the four clock management tiles in the Spartan-6. Each tile includes two Digital Clock Managers (DCMs) and four Phase-Locked Loops (PLLs).

Try this code instead:
 

Quote

 

module blink(
    input clk,
    input btnl,
    output led0
    );
    
    reg ledst0;
    reg state;

    always @(posedge clk) begin
        state <= btnl;
        if (btnl & ~state)
            ledst0 <= !ledst0;
    end
    
    assign led0 = ledst0;

endmodule

 

.ucf file:

Quote

NET "led0" LOC = U16;
NET "btnl" LOC = C4;
NET "clk" LOC = V10;

BTW, your switch might "bounce", so you might have to de-bounce the signal from the switch.
See What is debouncing?

Magnus

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