# Changing the clock frequency

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HELLO all,

just started my papilio journey and I need to reduce the 32MHz internal clock down to just 5Hz.

I tried reading materials about the CMT (clock management tile) but just got more confused.

thank u

Mar

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No, the CMT can't do that.  If some part of the logic needs to advance at a slow rate, the common way to do that is to use a clock-enable signal, i.e. clock the logic with the system clock (say 32 MHz) and then generate a clock-enable signal using a counter (in your case a 23-bit counter) that resets at the period you want (in your case at 6399999).  The clock-enable signal is true when the counter is at the max value (in your case 6399999) and is used to qualify the clocking of the slow circuit.

Hope this helps

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I asked around and realized that having the clock go through an inverted d flip flop divides the clock in half. I need 23 flip flops much like your 23-bit counter

Thank You!

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Just a quick comment that to generate a slower clock, a preferred method is to use a synchronous counter. This type of counter has all counter flops clocked by the same high speed input clock and fits well with the way that FPGAs handle clocks. It is also the way that this type of circuit would be designed in an ASIC.

Here is some code I wrote recently (as an example). It divides 315MHz from a PLL to 3.57MHz. A divide by 88 is required.

```reg [6:0] pll315_counter;

reg clk357;

// create 3.57MHz NTSC clock by dividing 315MHz by 88
always @ (posedge w_clk315) begin
clk357 <= (pll315_counter<7'd44);
if (pll315_counter==7'd87) begin
pll315_counter <= 7'b0;
end else begin
pll315_counter <= pll315_counter + 7'b1;
end
end```

You would need to change the counter length, termination count and half count to suit your frequencies. I should have really used constants (such as tick defines) rather than hard code numbers, but hey this is my personal hobby project 😃

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