mchowder

Changing the clock frequency

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HELLO all,

just started my papilio journey and I need to reduce the 32MHz internal clock down to just 5Hz.

I tried reading materials about the CMT (clock management tile) but just got more confused.

thank u 

Mar

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No, the CMT can't do that.  If some part of the logic needs to advance at a slow rate, the common way to do that is to use a clock-enable signal, i.e. clock the logic with the system clock (say 32 MHz) and then generate a clock-enable signal using a counter (in your case a 23-bit counter) that resets at the period you want (in your case at 6399999).  The clock-enable signal is true when the counter is at the max value (in your case 6399999) and is used to qualify the clocking of the slow circuit.

Hope this helps

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I asked around and realized that having the clock go through an inverted d flip flop divides the clock in half. I need 23 flip flops much like your 23-bit counter 

Thank You!

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