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martinayotte

JTAG JP4

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I've read this topic :

Quote

..."The Papilio Pro includes a reset header (JP4 ) that can be populated with a jumper to hold the Spartan 6 FPGA in permanent reset mode. This frees up theJTAG Header to be used as an FT2232JTAG /SPI/MPSSE Programmer." 

Unfortunately, this is NOT true !

Even if JP4 jumper is installed, either the papilio-prog or sc3sprog tools will report the presence of the LX9, this means the JTAG TDO line of LX9 is not in tri-state and will respond to any JTAG commands. The JTAG header is in parallel with the LX9, so any external JTAG devices will have their TDO in parallel with LX9 producing garbage communication returned to FT2232 input, which is exactly what papilio-prog or sc3sprog tools are showing : mixtures of collisions of bits returned by 2 devices fighting each others.

The workaround would be to have both LX9 and external devices placed in JTAG daisy chain like most design provide, having each devices TDI attached to previous TDO and the last TDO returned to the FT2232, but it is not how the PapilioPro is routed ...

So, conclusion, PapilioPro JTAG header is completely useless for programming external devices ...

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