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Programming the flash of Papilio PRO with a new FPGA application will require erasing the flash or a part of it.

My question is:
How much will be erased? The entire flash or only so many blocks that the application will occupy? Or "something in between", e.g. "always 2 MBits"? Or the number of blocks occupied ny the greatest possible application for SPARTAN6, by assumption different for ...LX4 and ...LX9?

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Thank you for the info, Thomas Hornschuh. It was as I hoped. But what do you mean by "Normally"? Are there cases when the entire flash is erased?

Anybody who knows or has an idea about the "worst-case" size of a SPARTAN6-LX9 bitstream? I.e. the size of the bitstream for the largest possible SPARTAN6-LX9 application.

 

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11 hours ago, dindea said:

Thank you for the info, Thomas Hornschuh. It was as I hoped. But what do you mean by "Normally"? Are there cases when the entire flash is erased?

 

A non compressed bitstream has always the same size which directly relates to the type of fpga. For a spartan-6 lx9 it is around 330KByte (when I remember it right, I‘m currently traveling so I cannot check). But it is possible to attach additional data to the bitstream e.g. with a program like bitmerge http://hamsterworks.co.nz/mediawiki/index.php/Config_flash

or the -a option of papilio-prog

This additional data can than be read with a spi flash interface added to the fpga design. 

I‘m not sure if papilio-prog erase always sectors (64KB) or pages (4KB). The flash chip on the Papilio Pro supports both. Anyway, when I use the flash in the Papilio Pro for own data I always start at 512KB, this is on the save side.

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