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Lockups when trying to write to Wishbone register.

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Hi! I'm trying to create a library based on the "Wishbone VHDL" sample i think.

I'm currently stuck trying to write to a wishbone register, the ZPUIno just locks up while the vhdl-module continues to happily tick without any noticeable changes.

I've cross-referenced my code with the simple writeLeds example but I really can't see anything that should cause this lockup, please help!. ( btw I'm on an Papilio Pro board )

Here's my code:http://www.pcbindex.com/

I can see the print of line 13 just fine, line 14 initiates the write, and then it gets stuck and I never seems to reach line 15

https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/examples/simple_tremolo/simple_tremolo.ino#L15

which goes to:

https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/DSP_Wing.cpp#L33  <- how i perform the actual register write

https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/DSP_Wing.vhd#L98 <-- Here i try to receive/read.

and finally..

https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/tremolo.vhd#L68 <-- unpack and act upon the command. but that never happens either, so i can only assume that something went wrong with the register write inside the zpuino and that the changes to the register were never applied.

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Hi,

The code up until the last part looks quite similar to that I have done.

https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/tremolo.vhd#L68

starts looking fishy.

* Normally.. simply always use rising edges (and specially of the clock)

* Your current process will only be "woken" up on a single bit transition(the control bit) but this will never happen unless you enable line 34 again..

https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/tremolo.vhd#L68

 

 

 

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