keesj Posted April 4, 2018 Report Share Posted April 4, 2018 Hi, I have been working on my first VHDL library for the papillio. Things are starting to work but I have a few annoyances/things I do not understand: 1) When I create a new wishbone library (from VHDL) I en up with the edit_library.ino file that offers me different options like (Define your chip) e.g. sketchdir://Chip_Designer.xise Should that code be able to compile/syntax check? I always end up with ERROR: Could not find symbol "mylib_wb" or similar when I press the green arrow 2) When I edit the target specific files e.g. sketchdir://circuit/PSL_Papilio_Pro_LX9.xise for example I alway have to "re-add" my vhdl files into the DesignLab library. How do I fix this issue? Quote Link to comment Share on other sites More sharing options...
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