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Contradiction in description

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The description (on 'papilio.cc') text for Papilio PRO "says":

  • Channel A is connected to the Papilio Pro in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
  • Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS).

But I think that the USB schematic right below the text "says" the reverse. The JTAG-s go to ADBUS0..3, TXD abd RXD go to BDBUS0..1. And so says the published complete schematics for Papilio PRO.

I am designing an own board based on ideas from the Papilio PRO schematics. I would rather really use Channel B for JTAG and channel A for data transfer. For then I can, with FT2232H as USB ctircuit, use synchronous FIFO245 for general data transfer. Only Channel A (FT2232H) supports synchronous FIFO245.

How is the FPGA code uploaded into the flash? Is it all over the JTAG interface, or is it by implanting an application which reads data from the UART (RS) channel, writing them into the flash memory word by word?
If the second is the truth, can Developement Studio handle the "reversed" USB addresses (COM ports, or...?)?

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JTAG only works on Channel A of the FT2232 that is used on the Papilio Pro because MPSSE is only available on Channel A. The newer FT2232H has MPSSE on both channels so it should work to switch them around. Just double check the datasheet and make sure MPSSE is supported. 

Jack.

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I have double-checked. MPSSE is supported on channel B.

How are the Flash data trnsferred to the Papilio Pro? Over the JTAG interface of ch.A or over the ASYNC (RS232) interface of ch.B? Is it a "bootstrap" procedure, where a "bootstrap" is first uploaded in the FPGA, this "bootstrap" then reading data from JTAG or ASYNC (which?) and writing into Flash.
Will Developement Studio unravel a situation where the A and B channels have changed places?

SC

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It's not bootstrap, a bit file gets loaded to the FPGA that connects the SPI pins of the Flash chip to the MPSSE engine of the FT2232 chip. papilio-prog is a fork of xc3sprog application. xc3sprog supports changing the channel.

Jack.

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It's a pity that the FTDI programmer can't be disconnected from the JTAG pins of the FPGA. I was given an old Xilinx FPGA board with the 1mm pitch header, but I was unable to do anything with it, because I didn't have a Xilinx programmer. At least in the UK on Ebay these are quite expensive. There are Altera programmers on Ebay and they are very cheap indeed. I searched for a FDTI 2232 board on Ebay, but suprisingly they are quite rare (although I did spot one for $10 in Hong Kong). If a new Papilio board is ever made, it would be a great feature (for some people at least) if there was a way to use the programmer stand-alone.

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19 hours ago, Jack Gassett said:

Yes, agreed.

Jack.

Hi,

In my 'Mariposa S6' design, I have inserted buffers at  the TMS and TCK inputs of the FPGA. The buffers are enabled/disabled by a "JTAG disable" pin on the board. The purpose of these buffers was from the beginning a "security lock" against "accidental" programming (changes of the FPGA code), e.g. because of contact bounces when the unit is powered-on and/or the JTAG cable is plugged-in or unplugged. The enable is delayed with a RC lag.

The signal paths from the JTAG circuit to the JTAG connector are still intact when the buffers are disabled. This means that the Mariposa S6 can be used as a "universal" JTAG programmer for other devices, also when "he" is up and running.

I think that you could fix such a feature to use the Papilio Pro as a "universal" JTAG programmer. Solder a couple of patch wires, to the FPGA's 'INIT_B' pin and GND, glue a 2-pole connector "somewhere" on the board. Insert a jumper to hold  the FPGA "permanently" reset. See attached schematics. The signal paths from USB circuit to JTAG connector will be "un-touched".

On the Papilio One the INIT_B pin is a multi-funcyional pin. It will be 'INIT_B' as long as the FPGA code is not uploaded, it becomes 'W1-B15' when the code is uploaded. Certainly: Connect it to GND before power-on. Then, certainly, the FPGA will be held in "permanent" reset. Signal paths from USB circuit to JTAG connector will be "un-touched".

Both boards: When the FPGA is held in permanent reset, the board can be used aas a general JTAG programming adapter.

/SC

JTAGpatch.pdf

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